- A development environment for configurable computing B. Boysen, N. DeBardeleben, K. M. Hazelwood, W. B. Ligon III,
- ParaWeaver: Performance Evaluation on Programming Models for Fine Grained Threads
- COVER FEATURE Published by the IEEE Computer Society 0018-9162/10/$26.00 2010 IEEE
- Improving Instrumentation Speed via Buffering Kim Hazelwood
- Enabling Task Parallelism in the CUDA Scheduler Marisabel Guevara Chris Gregg Kim Hazelwood Kevin Skadron
- Generational Cache Management of Code Traces in Dynamic Optimization Systems
- A Dynamic Binary Instrumentation Engine for the ARM Architecture
- Improving Indirect Branch Translation in Dynamic Binary Translators
- Characterizing Inter-Execution and Inter-Application Optimization Persistence
- A Cross-Layer Approach to Heterogeneity and Reliability Daniel Williams Aprotim Sanyal1
- The Interaction among the OS, the Compiler, and Multicore Processors Special Issue of ACM Operating System Review
- A Reactive Unobtrusive Prefetcher for Multicore and Manycore Architectures
- A Cross-Architectural Interface for Code Cache Manipulation Kim Hazelwood
- Reducing Exit Stub Memory Consumption in Code Caches
- Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization
- Contention-Aware Scheduling of Parallel Code for Heterogeneous Systems
- Creating Applications in RCADE Kim Hazelwood Walter B. Ligon III Greg Monn Natasha Pothen Ron Sass
- Where is the Data? Why You Cannot Debate CPU vs. GPU Performance Without the Answer
- Zsim: A Fast Architectural Simulator for ISA Design-Space Exploration
- Analyzing Program Flow within a Many-Kernel OpenCL Application
- Improving Region Selection Through Loop Completion Derek M Davis and Kim Hazelwood
- Balancing Memory and Performance through Selective Flushing of Software Code Caches
- Design of a Custom VEE Core in a Chip Multiprocessor Dan Upton and Kim Hazelwood
- Scalable Support for Multithreaded Applications on Dynamic Binary Instrumentation Systems
- Evaluating the Impact of Dynamic Binary Translation Systems on Hardware Cache Performance
- Trace Fragment Selection within Method-based JVMs Duane Merrill Kim Hazelwood
- Heterogeneous Chip Multiprocessor Design for Virtual Machines
- Managing Bounded Code Caches in Dynamic Binary Optimization Systems
- Adaptive Online Context-Sensitive Inlining Kim Hazelwood
- Code Cache Management Schemes for Dynamic Optimizers Kim Hazelwood Michael D. Smith
- Code Cache Management in Dynamic Optimization Systems
- HAZELWOOD, KIM MICHELLE Dynamic Optimization Infrastructure and Algorithms for IA-64
- "!#%$'&)(0214365879 A@B7C#D!EF3GIH PRQSQUTWVYXa`cb8Qedf`4ghV
- *Intel and the Intel logo are registered trademarks of Intel Corporation. Other brands and names are the property of their respective owners The Concurrent Collections (CnC) Parallel Programming
- Building Memory-efficient Java Applications: Practices and Challenges
- Fiveyearsonthefacultyat CurrentlyAssociateProfessorat
- Feedback-Directed Query Optimization Kim Hazelwood
- DBT Path Selection for Holistic Memory Efficiency and Performance
- Challenges and Opportunities at All Levels Interactions Among Operating Systems, Compilers, and Multicore Processors
- Next Generation Software Configuration Management System
- Process-Level Virtualization for Runtime Adaptation of Embedded Software
- Dynamic Program Analysis of Microsoft Windows Applications Alex Skaletsky, Tevi Devor, Nadav Chachmon, Robert Cohn, Kim Hazelwood, Vladimir Vladimirov, Moshe Bach
