- Procedural Texture Mapping on FPGAs Andy G. Ye and David M. Lewis *
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, JANUARY 2010 95 Using the Minimum Set of Input Combinations to
- Ph.D. Thesis Proposal: Routing Architecture and Place and Route Tools for DP-FPGA
- This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
- THE EFFECT OF SPARSE SWITCH PATTERNS ON THE AREA EFFICIENCY OF MULTI-BIT ROUTING RESOURCES IN
- A SCALABLE ARCHITECTURE FOR VARIABLE BLOCK SIZE MOTION ESTIMATION ON FIELD-PROGRAMMABLE GATE ARRAYS
- As the logic capacity of FPGAs increases, they are being used to implement ever-larger applications. Large applications, whether they are CPUs, graphics processors, digital signal processors, or packet switching networks, typically contain a
- Ph.D. Progress Report ---Report #2 (March 2001 --March 2002)
- In this paper, we propose a new datapath-oriented FPGA archi-tecture that utilizes coarse-grain logic and routing resources to
- A SCALABLE COMPUTING AND MEMORY ARCHITECTURE FOR VARIABLE BLOCK SIZE MOTION ESTIMATION ON FIELD-PROGRAMMABLE GATE ARRAYS
- Procedural Texture Mapping on FPGAs Andy G. Ye and David M. Lewis
- Ph.D. Annual Monitoring Report by Andy Gean Ye
