Cook, Jeanine - Klipsch School of Electrical and Computer Engineering, New Mexico State University

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Cook, Jeanine - Klipsch School of Electrical and Computer Engineering, New Mexico State University

UNIPROCESSOR PERFORMANCE ANALYSIS OF A REPRESENTATIVE WORKLOAD OF SANDIA NATIONAL LABORATORIES'
COMPILER-DIRECTED FUNCTIONAL UNIT SHUTDOWN FOR MICROARCHITECTURE POWER OPTIMIZATION
CHARACTERIZATION AND CLASSIFICATION OF MODERN MICRO-PROCESSOR BENCHMARKS
MODELING EFFECTS OF SPECULATIVE INSTRUCTION EXECUTION IN A FUNCTIONAL CACHE SIMULATOR
TECHNIQUES FOR ACCELERATING MICROPROCESSOR SIMULATION
Compiler-Directed Functional Unit Shutdown for Microarchitecture Power Optimization
Improved Estimation for Software Multiplexing of Performance Counters
IMPROVING ACCURACY FOR SOFTWARE MULTIPLEXING OF ON-CHIP PERFORMANCE COUNTERS
Journal of Instruction-Level Parallelism 9 (2007) 1-13 Submitted 4/07; published 5/07 An Idealistic Neuro-PPM Branch Predictor
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach
Performance Modeling Using Monte Carlo Simulation Ram Srinivasan, Jeanine Cook
Fast, Accurate Microarchitecture Simulation Using Statistical Phase Detection
Toward Accurate Performance Evaluation using Hardware Counters
Toward Reducing Processor Simulation Time via Dynamic Reduction of Microarchitecture Complexity
UNDERSTANDING THE EFFECTS OF MICROARCHITECTURAL PARAMETERS ON THE UNIPROCESSOR PERFORMANCE OF
DYNAMIC DETECTION OF WORKLOAD EXECUTION PHASES
IntrinsicData Locality of Modern Scientific Workloads Sharath Ramanathan Ramkumar Srinivasan Jeanine Cook
Exploiting Benchmark Patterns for Efficient Microarchitecture Simulation
Neuro-PPM Branch Prediction Ram Srinivasan *, Eitan Frachtenberg, Olaf Lubeck, Scott Pakin, Jeanine Cook*
A FPGA Implementation of a MIPS RISC Processor for Computer Architecture Education
A New Paradigm for Optimizing Hybrid Simulations of Rare Event Modeling for Complex Systems