Kim, Chris H. - Department of Electrical and Computer Engineering, University of Minnesota

• Enhancing Beneficial Jitter Using Phase Shifted Clock DistributionPhase-Shifted Clock Distribution
• A High-Speed Variation-Tolerant Sub-Threshold Interconnect Technique
• INTRODUCTION Mechanical circulatory support system are widely used
• Silicon Odometers: On-Chip Test Structures for Monitoring Reliability Mechanisms and Sources of Variation
• IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 9, NO. 4, DECEMBER 2009 537 A Finite-Oxide Thickness-Based Analytical Model
• Fig. 1. DC Stress condition for conventional RO used for NBTI measurement in SiO2/poly-gate technology [1][2].
• Width-dependent Statistical Leakage Modeling for Random Dopant Induced
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 5, MAY 2011 787 An Array-Based Test Circuit for Fully Automated
• Modeling and Analysis of Leakage Induced Damping Effect in Low
• 598 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 5, MAY 2008 design can be easily expanded to a hierarchical 64-bit adder such that
• 2130 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 10, OCTOBER 2010 Circuit Design and Modeling Techniques for
• A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009 1785 A Voltage Scalable 0.26 V, 64 kb 8T SRAM With
• An Analytical Model for Negative Bias Temperature
• Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency
• A Voltage Scalable 0.26V, 64kb 8T SRAM i h V i T h iwith Vmin Lowering Techniques
• Larger-than-Vdd Forward Body Bias in Sub-0.5V Nanoscale CMOS
• An On-Die CMOS Leakage Current Sensor for Measuring Process Variation in Sub-90nm Generations
• A Process Variation Compensating Technique
• This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
• Distributed Active Decoupling Capacitors for On-Chip Supply Noise Cancellation in Digital VLSI Circuits
• Sleep Transistor Sizing and Control for Resonant Supply
• Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift
• Enhancing Beneficial Jitter Using Phase-Shifted Clock Distribution
• A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance Damping Jie Gu, Hanyong Eom, Chris H. Kim
• An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement
• NBTI-Aware Synthesis of Digital Circuits Sanjay V. Kumar
• An On-Chip NBTI Sensor for Measuring PMOS Threshold Voltage Degradation
• Sleep Transistor Sizing and Control for Resonant Supply Noise Damping
• 330 2007 IEEE International Solid-State Circuits Conference ISSCC 2007 / SESSION 18 / SRAM / 18.5
• A Multi-story Power Delivery Technique for 3D Integrated
• An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown Characterization
• A A B d T t Ci it fAn Array-Based Test Circuit for Fully Automated Gate DielectricFully Automated Gate Dielectric
• Figure 1. (a) Worst case SNM scenario. (b) SNM simulation results. Circuit Techniques for Ultra-Low Power Subthreshold SRAMs
• A Multi-Story Power Delivery Technique for 3D Integrated Circuits Pulkit Jain, Tae-Hyoung Kim, John Keane, Chris H. Kim
• Enhancing Beneficial Jitter Using Phase-Shifted Clock Distribution
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 3, MARCH 2008 249 Body Bias Voltage Computations for Process
• 456 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 4, APRIL 2008 A High-Speed Variation-Tolerant Interconnect
• 128 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 1, JANUARY 2009 Modeling, Analysis, and Application of Leakage
• Adaptive Techniques for Overcoming Performance Degradation due to Aging in Digital Circuits
• Circuit Techniques for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise
• 134 978-4-86348-010-0 2009 Symposium on VLSI Circuits Digest of Technical Papers A Sub-0.9V Logic-compatible Embedded DRAM with Boosted 3T Gain Cell,
• Printed, Sub-3V Digital Circuits on Plastic from Aqueous Carbon Nanotube
• ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 4, APRIL 2010 817 An All-In-One Silicon Odometer for Separately
• Introductory Invited Paper On-chip reliability monitors for measuring circuit degradation
• This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
• A 1.1V, 667MHz Random Cycle, Asymmetric 2T Gain Cell Embedded DRAM with a 99.9 Percentile Retention Time of 110sec
• 326 2011 IEEE International Solid-State Circuits Conference ISSCC 2011 / SESSION 18 / ORGANIC INNOVATIONS / 18.3
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 6, JUNE 2011 1495 A 3T Gain Cell Embedded DRAM Utilizing
• 28 NA iEEE SpEctrum mAy 2011 spectrum.ieee.org FFFFFF OOOOOO RRRRRR CCCCCC PPPPPP UUUUUU SSSSSS
• Mathematically Assisted Adaptive Body Bias (ABB) for Temperature Compensation in Gigascale LSI Systems
• Width Quantization Aware FinFET Circuit Design
• Leakage in Nano-Scale Technologies: Mechanisms, Impact and Design Considerations
• Subthreshold Logical Effort: A Systematic Framework for Optimal
• Self Calibrating Circuit Design for Variation Tolerant VLSI Systems Chris H. Kim
• Ultra-Low Power DLMS Adaptive Filter For Hearing Aid Applications
• Dynamic Vt SRAM : A Leakage Tolerant Cache Memory for Low Voltage Microprocessors
• A Forward Body-Biased Low-Leakage SRAM Cache: Device and Architecture Considerations
• Utilizing Reverse Short Channel Effect for Optimal Subthreshold Circuit Design
• Utilizing Reverse Short Channel Effect for Optimal Subthreshold
• Modeling and Analysis of Leakage Induced Damping Effect in Low Voltage LSIs
• 482 2005 IEEE International Solid-State Circuits Conference 0-7803-8904-2/05/$20.00 2005 IEEE. ISSCC 2005 / SESSION 26 / STATIC MEMORY / 26.5
• Effectiveness of Using Supply Voltage as Back-Gate Bias in Ground Plane SOI Chris H. Kim1
• A Process Variation Compensating Technique for Sub-90nm Dynamic Circuits Chris H. Kim, Kaushik Roy, Steven Hsu*, Atila Alvandpour*, Ram K. Krishnamurthy*, Shekhar Borkar*
• An On-Die CMOS Leakage Current Sensor for Measuring
• Leakage power analysis and reduction: models, estimation and tools
• CMOS devices have scaled down-ward aggressively in each technology genera-
• Abstract--As the clock frequency and physical address space of 64b microprocessors continue to grow, one major critical path is
• 716 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003 Gate Leakage Reduction for Scaled Devices
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 3, MARCH 2005 349 A Forward Body-Biased Low-Leakage SRAM Cache
• Impact of NBTI on SRAM Read Stability and Design for Reliability
• An Analytical Model for Negative Bias Temperature Instability Sanjay V. Kumar, Chris H. Kim, and Sachin S. Sapatnekar
• Variation Aware Performance Analysis of Gain Cell Embedded DRAMs
• Method for Qcrit Measurement in Bulk CMOS Using a Switched Capacitor Circuit
• NBTI-Aware Synthesis of Digital Circuits
• A Voltage Scalable 0.26V, 64kb 8T SRAM with Vmin Lowering Techniques and Deep Sleep Mode
• Fast and Accurate Estimation of Nano-Scaled SRAM Read Failure Probability using Critical Point Sampling
• Dynamic VTH Scaling Scheme for Active Leakage Power Reduction Chris H. Kim and Kaushik Roy
• 272 2011 IEEE International Solid-State Circuits Conference ISSCC 2011 / SESSION 15 / HIGH-PERFORMANCE SOCS & COMPONENTS / 15.5
• An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect
• Subthreshold Logical Effort: A Systematic Framework for Optimal Subthreshold Device Sizing
• Printed Sub-2 V Gel-Electrolyte-Gated Polymer Transistors and Circuits
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 7, JULY 2007 821 Utilizing Reverse Short-Channel Effect for Optimal
• 874 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 4, APRIL 2008 Silicon Odometer: An On-Chip Reliability Monitor
• 108 978-4-86348-010-0 2009 Symposium on VLSI Circuits Digest of Technical Papers An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB
• PVT-Aware Leakage Reduction for On-Die Caches with
• Width Quantization Aware FinFET Circuit Design Jie Gu, John Keane, Sachin Sapatnekar, and Chris Kim
• 206 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 2, FEBRUARY 2008 Transactions Briefs
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 4, APRIL 2011 603 Adaptive Techniques for Overcoming Performance
• A Switched Decoupling Capacitor Circuit for On-Chip Supply Resonance
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009 1765 On-Chip Supply Noise Regulation
• Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits
• 170 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 1, JANUARY 2006 PVT-Aware Leakage Reduction for On-Die Caches
• 292 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 2, FEBRUARY 2009 Design and Implementation of Active
• 1058 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 6, DECEMBER 2003 Ultra-Low-Power DLMS Adaptive Filter for
• 518 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008 A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells
• An On-Chip NBTI Sensor for Measuring PMOS Threshold
• A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage
• Distributed Active Decoupling Capacitors for On-Chip Supply Noise
• Fig. 1. Impact of NBTI and TDDB on read static noise margin of a 6T An SRAM Reliability Test Macro for Fully-Automated
• 506 2011 IEEE International Solid-State Circuits Conference ISSCC 2011 / SESSION 28 / DRAM & HIGH-SPEED I/O / 28.10
• TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique
• Fig. 1. System diagram. Reference ROSCs have 15 trimming capacitors controlled by the scan chain. Stressed ROSCs are taken out of stress
• A Multi story Power DeliveryA Multi-story Power Delivery Technique for 3D Integratedq g
• Measurement, Analysis and Improvement of Supply Noise in 3D ICs Pulkit Jain, Dong Jiao, Xiaofei Wang, Chris H. Kim
• Exploration of On-Chip Switched-Capacitor DC-DC Converter for Multicore Processors Using a Distributed Power Delivery
• 2374 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 10, OCTOBER 2011 An Array-Based Odometer System for Statistically
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 2, FEBRUARY 2012 547 A 667 MHz Logic-Compatible Embedded