- UNIVERSITY OF MINNESOTA This is to certify that I have examined this copy of a doctoral thesis by
- Efficient Architecture Support for Thread-Level Speculation SUBMITTED TO THE FACULTY OF THE GRADUATE SCHOOL
- Compiler Optimization of Scalar Value Communication Between Speculative Threads
- Issues and Support for Dynamic Register Abhinav Das, Rao Fu, Antonia Zhai, and Wei-Chung Hsu
- A General Compiler Framework for Speculative Optimizations Using Data Speculative Code Motion
- Supporting Speculative Multithreading on Simultaneous Multithreaded Processors
- Efficiency of Thread-Level Speculation in SMT and CMP Architectures -Performance, Power and Thermal Perspective
- Exploring Speculative Parallelism in SPEC2006 Venkatesan Packirisamy, Antonia Zhai, Wei-Chung Hsu, Pen-Chung Yew and Tin-Fook Ngai
- Loop Selection for Thread-Level Speculation Shengyue Wang, Xiaoru Dai, Kiran S. Yellajyosula,
- Exploiting Speculative Thread-Level Parallelism in Data Compression Applications
- Compiler Optimizations for Parallelizing General-Purpose Applications under Thread-Level Speculation
- Hardware Supported Flexible Monitoring: Early Results
- Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads
- Improving Value Communication for Thread-Level Speculation J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry
- A Scalable Approach to Thread-Level Speculation J. Gregory Steffan, Christopher B. Colohan, Antonia Zhai, and Todd C. Mowry
- Loop Selection for Thread-Level Speculation Shengyue Wang, Xiaoru Dai, Kiran S. Yellajyosula,
- A Study of the Performance Potential for Dynamic Instruction Hints Selection
- Dynamic Performance Tuning for Speculative Threads Yangchun Luo, Venkatesan Packirisamy,
