- Operating System Scheduling for Efficient Online Self-Test in Robust Systems
- Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
- THREAD CLUSTER MEMORY MEMORY SCHEDULERS IN MULTICORE SYSTEMS SHOULD CAREFULLY SCHEDULE
- Flexible Reference-Counting-Based Hardware Acceleration for
- Prefetch-Aware Shared-Resource Management for Multi-Core Systems
- Next Generation On-Chip Networks: What Kind of Congestion Control Do We Need?
- Efficient Runahead Threads Tanaus Ramrez
- Concurrent Autonomous Self-Test for Uncore Components in System-on-Chips Stanford University
- Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems
- Fairness via Source Throttling: A configurable and high-performance fairness
- ACCELERATING CRITICAL SECTION EXECUTION WITH ASYMMETRIC
- A Flexible Software-Based Framework for Online Detection of Hardware Defects
- A Case for Bufferless Routing in On-Chip Networks Thomas Moscibroda
- PARALLELISM-AWARE BATCH SCHEDULING: ENABLING
- Prefetch-Aware DRAM Controllers Chang Joo Lee Onur Mutlu Veynu Narasiman Yale N. Patt
- Distributed Order Scheduling and its Application to Multi-Core DRAM Controllers
- Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems
- Improving the Performance of Object-Oriented Languages with Dynamic Predication of Indirect Jumps
- Improving the Performance of Object-Oriented Languages with
- Performance-Aware Speculation Control using Wrong Path Usefulness Prediction
- Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths
- HPS Research Group The University of Texas at Austin
- Efficient Runahead Execution: Power-efficient Memory Latency Tolerance Onur Mutlu Hyesoon Kim Yale N. Patt
- Wish Branches: Enabling Adaptive and Aggressive Predicated Execution Hyesoon Kim Onur Mutlu Jared Stark Yale N. Patt
- Works when Load 1 and 2 are independent Load 1 Miss
- Fault Tolerance with Microarchitecture-Based Introspection
- Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors
- Wrong Path Events and Their Application to
- Wrong Path Events: Exploiting Illegal and Unusual Program Behavior for Early Misprediction Recovery
- Hyesoon Kim David N. Armstrong
- An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors
- Prefetch-Aware Shared-Resource Management for Multi-Core Systems Eiman Ebrahimi Chang Joo Lee Onur Mutlu Yale N. Patt
- Compiler-Assisted Dynamic Predicated Execution of Complex Control-Flow Structures
- Wish Branch: A New Control Flow Instruction Combining Conditional Branching and Predicated Execution
- EE 382N Literature Survey Onur Mutlu Memory Dependence Prediction and Access Ordering for Memory Disambiguation
- Implementation of Clocks and Sensors EE 382N Distributed Systems
- Music and Speed of Processing 1 BACKGROUND MUSIC AND SPEED OF PROCESSING
- A Low-Power Low-Cost Microcontroller for Security Systems
- A Grammatical Sketch of Even In this paper I would like to give a concise description of Even grammar, which is
- Memory Systems in the Many-Core Era: Challenges, Opportunities, and Solution Directions
- Coordinated Control of Multiple Prefetchers in Multi-Core Systems
- VPC Prediction: Reducing the Cost of Indirect Branches via Hardware-Based Dynamic Devirtualization
- Multimedia Systems Assignment #2
- AERGIA: A NETWORK-ON-CHIP EXPLOITING PACKET LATENCY SLACK
- A Case for MLP-Aware Cache Replacement Moinuddin K. Qureshi Daniel Lynch Onur Mutlu Yale N. Patt
- Project Report EE 371R Digital Image Processing
- SAFARI Technical Report No. 2010-001 (December 29, 2010) CHIPPER: A Low-complexity Bufferless Deflection Router
- Architecting Phase Change Memory as a Scalable DRAM Alternative
- Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
- Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References
- Application-Aware Prioritization Mechanisms for On-Chip Networks
- DATA MARSHALING FOR MULTICORE SYSTEMS
- Preemptive Virtual Clock: A Flexible, Efficient and Cost-effective QOS
- Performance-Aware Speculation Control Using Wrong Path Usefulness Prediction Chang Joo Lee Hyesoon Kim Onur Mutlu Yale N. Patt
- Application-to-Core Mapping Policies to Reduce Interference in On-Chip Networks
- Runahead Execution An Alternative to Very Large Instruction
- Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors Onur Mutlu Thomas Moscibroda
- The Dissertation Committee for Onur Mutlu certifies that this is the approved version of the following dissertation
- Self-Optimizing Memory Controllers: A Reinforcement Learning Approach Engin Ipek1,2
- Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction
- Multimedia Systems Project 3 Onur Mutlu November 2001 Chandresh Jain
- FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations
- Preemptive Virtual Clock: A Flexible, Efficient, and Cost-effective QOS Scheme for Networks-on-Chip
- FIST: A Fast, Lightweight, FPGA-Friendly Packet Latency Estimator for NoC Modeling in Full-System Simulations
- Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior
- Abstract This paper identifies non-stationary effects in grid like Network-on-Chip (NoC) traffic and proposes QuaLe, a novel
- Memory Performance Attacks: Denial of Memory Service in Multi-Core Systems
- Load 1 Miss Stall Compute
- Operating System Scheduling for Efficient Online Self-Test in Robust Systems Yanjing Li Onur Mutlu Subhasish Mitra
- Guest Editors' Introduction.................................................................................................................................................................................................................. ......As co-chair
- 2D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set Hyesoon Kim M. Aater Suleman Onur Mutlu Yale N. Patt
- Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently
- Appears in the Proceedings of the 38th International Symposium on Computer Architecture
- Efficient Runahead Threads Tanaus Ramrez
- Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses
- Reducing Memory Interference in Multicore Systems via Application-Aware Memory Channel Partitioning
- Memory Power Management via Dynamic Voltage/Frequency Scaling
- Memory Systems in the Many-Core Era: Some Challenges and Solution Directions
- SAFARI Technical Report No. 2011-003 (July 20, 2011) Congestion Control for Scalability in Bufferless On-Chip Networks
- SAFARI Technical Report No. 2011-007 (September 6, 2011) A High-Performance Hierarchical Ring On-Chip Interconnect with
- SAFARI Technical Report No. 2011-004 (August 29, 2011) Investigating the Viability of Bufferless NoCs
- SAFARI Technical Report No. 2011-006 (September 6, 2011) Adaptive Cluster Throttling: Improving High-Load Performance in
- SAFARI Technical Report No. 2011-005 (September 5, 2011) Row Buffer Locality-Aware Data Placement in Hybrid Memories
- Improving GPU Performance via Large Warps and Two-Level Warp Scheduling
- Prefetch-Aware Memory Controllers Chang Joo Lee, Student Member, IEEE, Onur Mutlu, Member, IEEE,
- Bottleneck Identification and Scheduling in Multithreaded Applications
- A New Algorithm for Fast and Comprehensive
- 978-3-9810801-8-6/DATE12/2012 EDAA Error Patterns in MLC NAND Flash Memory
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