- Bericht ber Arbeiten zu Asynchronen Wave Pipelines Stephan Hermanns und Sorin Alexander Huss
- TWO-PHASE ASYNCHRONOUS WAVE-PIPELINES AND THEIR APPLICATION TO A 2D-DCT
- Bericht ber Arbeiten zu Asynchronen Wave Pipelines Stephan Hermanns und Sorin Alexander Huss
- A highly efficient modular Multiplication Algorithm for Finite Field Arithmetic in GF(P)
- A Novel Specification Model for IP-based Design Stephan Klaus and Sorin A. Huss
- EFFICIENT AND SAFE ASYNCHRONOUS WAVE-PIPELINE ARCHITECTURES FOR DATAPATH AND CONTROL UNIT APPLICATIONS
- An Efficient Approach to Switching Activity Estimation in Finite State Machines
- SAME 2001, November 15th A combinatorial logic block of a synchronous
- Effiziente Mixed-Level Modellierung integrierter Mixed-Signal Automotive Schaltkreise
- EXTENDED TIME HANDLING STRATEGIES FOR THE IMPROVEMENT OF PREDICTION ACCURACY IN EVENT
- ASYNCHRONOUS WAVE-PIPELINES WITH IMPROVED LOGIC AND LATCH CIRCUITS
- xCDM Ein interaktives Werkzeug zur graphenbasierten Systemmodellierung
- Specification and Validation of Information Processing Systems by Process Encapsulation and Symbolic Execution
- Automed'99 34 Modellierung & Simulation Modellierung nichtlinearer Systeme
- Interrelation of Specification Method and Scheduling Results in Embedded System Design
- Komponentenbasierte Mixed-Level-Modellierung mit variablen MOSFET-Verhaltensmodellen
- A high-level approach to power estimation of digital circuits at an ac-curacy of transistor-level simulation
- VLSI System Design Using Asynchronous Wave Pipelines: A 0.35 m CMOS 1.5 GHz Elliptic Curve Public Key Cryptosystem Chip
- High Level Spezifikationen f ur eingebettete Systeme
- HARDWARE TROJANS: Data Leakage Using General
- Real Time Image Processing based on Reconfigurable Hardware Acceleration
- Cyclic process nets as a highlevel behavioral specification model for embedded systems synthesis
- ASYNCHRONOUS VLSI ARCHITECTURES FOR HUFFMAN CODECS O. Hauck, H. Sauerwein, and S. A. Huss
- ASYNCHRONOUS WAVE PIPELINES FOR HIGH THROUGHPUT DATAPATHS
- Optimized Implementation of Elliptic Curve Based Additive Homomorphic Encryption for Wireless Sensor Networks
- Verifikation der Testschaltung und Simulation der Prf-vorschrift eines Automotive ICs
- Sorin A. Huss, Technische Universitt Darmstadt, Germany (Ed.) Advances in Design and Specification
- Resource Management for Dynamic Reconfigurable Hardware Structures
- Hocheffiziente modulare Multiplikation fur GF(P) Rainer Blumel, Ralf Laue und Sorin A. Huss
- A Case Study on Partial Evaluation in Embedded Software Design Michael Jung, Ralf Laue, and Sorin Alexander Huss
- Automatic Generation of Executable Models from Structured Approach Real-Time Specifications
- Huss, S.A., Jung, M. and Madlener F. Germany, Darmstadt University of Technology, Integrated Circuits and Systems Lab.
- Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach
- A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over
- Einleitung und Motivation Elliptische Kurven haben im Bereich der Public-
- 10. E.I.S. Workshop, Dresden, April 2001. Ein FPGA basierter Elliptic-Curve Kryptoprozessor mit variabler
- ekompressionsrechner messen den auf den Taucher einwir-
- Modellierung gemischt analog/digitaler Schaltungen mit VHDL-AMS S. A. Huss, S. Klupsch und R. Rosenberger
- Synthesizing massive parallel simulation systems to estimate switching activity in finite state machines
- High Level Simulation groer digitaler Schaltungen zur Be-stimmung der Leistungsaufnahme
- An Integrated SystemC Framework for Real-Time Scheduling Assessments on System Level
- Modellierung Modellierung
- A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks
- Rapid Prototyping for Hardware Accelerated Elliptic Curve Public-Key Cryptosystems
- Fast Points-to Analysis for Languages with Structured Types
- A Reconfigurable Coprocessor for Finite Field Multiplication in GF(2n M. Jung, F. Madlener, M. Ernst and S. A. Huss
- Estimation of signal activity in digital circuits based on multiple abstraction levels and massive parallel simulation techniques
- SAME 2001, November 15 th 2001 1 A combinatorial logic block of a synchronous
- Giga-Hertz SRT-Division mit asynchronen Wave-Pipelines O. Hauck, Integrierte Schaltungen und Systeme, TU Darmstadt
- GMM -ITG -GI Workshop Multi-Nature Systems '99 Optimierung der Modellbildung
- Functional Speci cation of Distributed Digital Image Processing Systems by Process Interface Descriptions
- 8. E.I.S.Workshop am 8. und 9. April 1997 an der Universit at Hamburg Intervallbasiertes Scheduling von Prozenetzen f ur
- Technical Report TUD-CS-2008-1103
- Gleichzeitig mit der Integra-tionsdichte neuer Generationen
- Design Space Exploration of incompletely specified Embedded Systems by Genetic Algorithms
- A Novel Multiple Core Co-Processor Architecture for Efficient Server-based Public Key Cryptographic Applications
- Automatic Generation of Scheduled SystemC Models of Embedded Systems From Extended Task Graphs
