- A testability enhancement technique for improving the test ability of a behaviorallevel VHDL specification is proposed.
- Test Resource Partitioning and Optimization for SOC Designs Erik Larsson+* and Hideo Fujiwara*
- Linkping Studies in Science and Technology Submitted to the School of Engineering at Linkping University in partial
- Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
- This paper deals with test parallelization (scan-chain sub-division) which is used as a technique to reduce test application
- Integrating Core Selection in the SOC Test Solution Design-Flow Erik Larsson
- The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test
- A behavioral testability analysis technique is proposed for early prediction of testability by analyzing behavioral spec
- Sveriges Ingenjrer bildades d Civilingenjrsfrbundet och Ingenjrsfrbundet gick samman 1/1 2007.
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 3, MARCH 2006 305 Transactions Briefs
- We propose a technique for test scheduling and design of test bus infrastructure where test application time as well as
- Efficient Embedding of Deterministic Test Data Mudassar Majeed1, Daniel Ahlstrom1, Urban Ingelsson1, Gunnar Carlsson2 and Erik Larsson1
- Optimized Integration of Test Compression and Sharing for SOC Testing
- Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding Pramod Subramanyan Virendra Singh Kewal K. Saluja Erik Larsson
- We propose an integrated technique for extensive optimization of the final test solution for System-on-Chip
- Lecture 1.3 INTERNATIONAL TEST CONFERENCE 1 1-4244-1128-9/07/$25.00 2007 IEEE
- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
- Core-Level Compression Technique Selection and SOC Test Architecture Design1
- Integrated Test Scheduling, Test Parallelization and TAM Design Erik Larsson+
- Test Quality Analysis and Improvement for an Embedded Asynchronous FIFO
- Published in IET Computers & Digital Techniques Received on 15th May 2007
- Early Prediction of Testability by Analyzing Behavioral VHDL Specifications Erik Larsson and Zebo Peng
- An Architecture for Combined Test Data Compression and Abort-on-Fail Test Erik Larsson and Jon Persson
- On Minimization of Peak Power for Scan Circuit during Test Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, and Vishwani D. Agrawal
- Power Constrained Preemptive TAM Scheduling Erik Larsson and Hideo Fujiwara
- Test Design for Computer Systems with Life-Time Perspective Project 05.06
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 5, MAY 2008 973 Cycle-Accurate Test Power Modeling and Its Application
- Test data truncation for test quality maximisation under ATE memory depth constraint
- Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process
- JOURNAL OF ELECTRONIC TESTING: Theory and Applications 21, 651658, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The United States.
- JOURNAL OF ELECTRONIC TESTING: Theory and Applications 21, 599611, 2005 c 2005 Springer Science + Business Media, Inc. Manufactured in The United States.
- 758 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 Efficient Test Solutions for Core-Based Designs
- Measurement Point Selection for In-Operation Wear-Out Monitoring
- On Scan Chain Diagnosis for Intermittent Faults Dan Adolfsson
- Fault-Tolerant Average Execution Time Optimization for General-Purpose Multi-Processor System-On-Chips
- A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
- SOC Test Scheduling with Test Set Sharing and Broadcasting Anders Larsson, Erik Larsson, Petru Eles and Zebo Peng
- Paper 32.2 INTERNATIONAL TEST CONFERENCE 1 0-7803-9039-3/$20.00 2005 IEEE
- Defect-Aware SOC Test Scheduling Erik Larsson+, Julien Pouget*, and Zebo Peng+
- Optimal System-on-Chip Test Scheduling Erik Larsson*+
- An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
- Linkping Studies in Science and Technology Department of Computer and Information Science
- Design Automation for IEEE P1687 Farrokh Ghani Zadegan1, Urban Ingelsson1, Gunnar Carlsson2 and Erik Larsson1
- SOC Test Time Minimization Under Multiple Constraints Julien Pouget, Erik Larsson, and Zebo Peng
- JOURNAL OF ELECTRONIC TESTING: Theory and Applications 18, 385400, 2002 c 2002 Kluwer Academic Publishers. Manufactured in The Netherlands.
- A technique to schedule tests for complex digital systems is proposed where the test application time is minimized while the power dissipation is kept under control. The
- ATECHNIQUEFOR TESTINFRASTRUCTURE DESIGNANDTESTSCHEDULING Erik Larsson and Zebo Peng
- An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint
- An IntegratedSystem-On-ChipTest Framework Erik Larsson and Zebo Peng
- Combined Test Data Compression and Abort-on-Fail Testing Erik Larsson
- Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are
- Defect Probability-based System-On-Chip Test Scheduling Erik Larsson, Julien Pouget and Zebo Peng
- Linkping Studies in Science and Technology Department of Computer and Information Science
- What Impacts Course Evaluation? Erik Larsson, Medhi Amirijoo, Daniel Karlsson, Petru Eles
- A Distributed Architecture to Check Global Properties for Post-silicon Debug
- A Controller Testability Analysis and EnhancementTechnique Synopsys,Inc.
- Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip
