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- Scalable Computing: Practice and Experience Volume 9, Number 3, pp. 185196. http://www.scpe.org
- A Power Efficient Reconfigurable Max-Log-MAP Turbo Decoder for Wireless Communication Systems
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- IP 2000 Conference 23. / 24. October 2000 Page 1 25/8/00
- IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 49, NO. 3, MARCH 2002 223 Therefore, matching like powers in (68), we get
- Mapping Real Time Operating System on Reconfigurable Instruction Cell Based Architectures
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- Multiple Input Multiple Output (MIMO) wireless technology involves highly complex signal processing
- Multiple Input -Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix
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- Power Driven Routing Using a Genetic Algorithm B. M. Goni, T. Arslan
- IEE UK Low Power Forum, September 1998, Sheffield, UK, pp. 7.17.5 Low Power Implementation of Direct Form FIR filters on DSPs
- An Improved Particle Swarm Optimization Algorithm for Power-Efficient Wireless Sensor Networks
- A LOW POWER FIR FILTERING CORE A. T. Erdogan, M. Hasan and T. Arslan
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- ELECTRONICS LETTERS 10th December 1998 Vol. 34 No. 25 Low power DCT implementation approach
- IEE Electronics Letters, vol. 34, no. 19, pp. 18171819, 1998. A Lowpower Coefficient Segmentation Algorithm for FIR Filter Implementation
- IEEE International Symposium on Circuits and Systems (ISCAS'97), Hong Kong, 912 June 1997, pp. 19401943. Low Power Multiplication Schemes for Single Multiplier CMOS Based FIR Digital Filter
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- A Novel Architecture Using the Decorrelating Transform for Low Power Adaptive Filters
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- The University of Edinburgh System Level Integration Group
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- the Integrated Intelligent Secure Sensor Systems project A.B.T. Hopkins and
- Multiple Input -Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix
- 1-4244-0910-1/07/$20.00 2007 IEEE. Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications
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- A RECONFIGURABLE VITERBI TRACEBACK FOR IMPLEMENATION ON TURBO DECODING ARRAY
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- Adaptive Micro-Antenna on Silicon Substrate Nakul Haridas1
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- Abstract--Weight and size are the bottlenecks of portable wireless systems which are in turn dependent on area and
- Image Registration of Printed Circuit Boards using Hybrid Genetic Syamsiah Mashohor1
- A Multi-objective Genetic Algorithm for On-chip Real-time Adaptation of a Multi-Carrier based Telecommunications Receiver
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- A Stochastic Multi-Objective Algorithm for the Design of High Performance Reconfigurable Architectures
- Abstract--This paper introduces a new methodology for the design of finite impulse response filters within an evolvable
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- Domain-specific heterogeneous reconfigurable arrays are for one particular domain of applications, which
- A Low-Power Reconfigurable Datapath for Advanced Speech Coding Algorithms Konstantinos Katsoulakis1
- A Domain Specific Reconfigurable Viterbi Fabric for System-On-Chip Applications
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- Implementation of an Efficient Two-Step SOVA Turbo Decoder for Wireless Communication Systems
- Power and Area Efficient Turbo Decoder Implementation for Mobile Wireless Systems
- IMPROVED MEMORY STRATEGY FOR LOGMAP TURBO DECODERS Imran Ahmed t,2 Tughrul Arslan1'2, Sajid Baloch1'2
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- The Development of High Performance FFT IP Cores through Hybrid Low Power Algorithmic Methodology
- Inter-wire coupling is a major source of power consumption and delay faults for on-chip buses
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- Synthesizable Reconfigurable Array Targeting Distributed Arithmetic for System-on-Chip Applications
- Reconfigurability-Power Trade-Offs in Turbo Decoder Design and Implementation
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- Energy Evaluation Methodology for Platform Based System-On-Chip Design Kristian Hildingsson1
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- Node and Network Architecture for Wireless Pic0 Systems Yiming Wang', K. Sivansed, and TughrulArslan'?
- Frequency and Scale Domain Analysis of Complex Quadrature Embolic Doppler UltrasoundSignals
- A TRIPLEPORT RAM BASED LOW POWER COMMUTATOR ARCHITECTURE FOR A PIPELINEDFFT PROCESSOR
- Proc of the 4th Annual IEEE Conf on InformationTechnologyApplicationsin Biomedicine,UK DIRECT SEQUENCE CDMA BASED WIRELESS INTERFACEFOR AN
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- Low Power Embedded Extension Algorithm for the Lifting based Discrete Wavelet Transform in JPEG2000
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- IEEE TRANSACTIONS ON EVOLUTIONARY COMPUTATION, VOL. 5, NO. 1, FEBRUARY 2001 27 Synthesis of Low-Power DSP Systems Using a
- Rule Evolution in Order based Diagnostic Systems Robert I. Graham and Tughrul Arslan
- $)0&13245 ! "687!9 A. C. McCormick, P. M. Grant, J. S. Thompson, T. Arslan and A. T. Erdogan
- A Novel Genetic Algorithms for the Automated Design of Performance Driven Digital Circuits
- A Novel Evolvable Hardware Framework for the Evolution of High Performance Digital Circuits
- A COEFFICIENT SEGMENTATION ALGORITHM FOR LOW POWER IMPLEMENTATION OF FIR FILTERS
- Segmentation Strategies for Low Power Implementation of Digital Filters T. Arslan and A. T. Erdogan
- LOW POWER DCT IMPLEMENTATION APPROACH FOR VLSI DSP PROCESSORS S. Masupe and T. Arslan
- IEEE Int. Symposium on Circuits and Systems (ISCAS '98), Monterey, CA, USA, July 1998. 1998 IEEE. Personal use of this material is permitted However, permission to reprint/republish this material for advertising or promotional purposes or for creating ne
- PII: S0026-2692(96) 00010-9 MicroelectronicsJournal27 (1996) 731-744
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- Genetic Algorithm based Engine for Domain-Specific Reconfigurable Arrays Wing On Fung1
- STATE-SPACETECHNIQUEFOR MINIMALREALISATIONOF ANALOGUECIRCUITSAND SYSTEMS University of Hull
- INTEGRATING THE ELECTRONICS OF THE CONTROL-LOOPS OF THE JPL/BOEING GYROSCOPE WITHIN AN EVOLVABLE HARDWARE ARCHITECTURE
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- E. Macii et al. (Eds.): PATMOS 2004, LNCS 3254, pp. 585592, 2004. Springer-Verlag Berlin Heidelberg 2004
- IEE Colloquim on Low Power Analogue and Digital VLSI: ASICs, Techniques and Applications, 2 June 1995, pp. 493498. OVERVIEW AND DESIGN DIRECTIONS FOR LOWPOWER CIRCUITS AND ARCHITECTURES FOR
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- Proceedingsof the 25' Annual InternationalConferenceof the IEEE EMBS Caneun,Mexico * September 17-21,2003
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- Low power multi-segment sequential one hot addressing architecture
- AN EFFICIENT FAULT TOLERANCE SCHEME FOR PREVENTING SINGLE EVENT DISRUPTIONS IN RECONFIGURABLE ARCHITECTURES
- 182 IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE, VOL. 8, NO. 2, JUNE 2004 Embolic Doppler Ultrasound Signal Detection Using
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- IEEE International Symposium on Circuits and Systems (ISCAS'98), 31 May --3 June 1998, Monterey, CA, pp. D425D428. LOW POWER IMPLEMENTATION OF LINEAR PHASE FIR FILTERS
- IEEE International Symposium on Circuits and Systems (ISCAS'98), 31 May --3 June 1998, Monterey, CA, pp. D441D444. DATA BLOCK PROCESSING FOR LOW POWER IMPLEMENTATION OF DIRECT FORM FIR FILTERS ON
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- LOW POWER DOMAIN-SPECIFIC RECONFIGURABLE ARRAY FOR DISCRETE WAVELET TRANSFORMS TARGETING MULTIMEDIA APPLICATIONS
- Techniques for the Evolution of Pipelined Linear Transforms Robert Thomson and TIghrul Arslan
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- A Genetic Algorithmfor Energy Efficient Device Schedulingin Real-Time Lirong Tian' and 'hghrul Arslan't
- A Real Time Programmable Encoder for Low Density Parity Check Code as specified in the IEEE P802.16E1D7 Standard and its
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- Efficient Implementations of Mobile Video Computations on Domain-Specific Reconfigurable Arrays
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- Simulating Photonic Bandgap Antennas on Silicon Substrate Nakul Haridas', Ahmet T. Erdogan" 2, Anthony J. Walton', Tughrul Arslan"2
- Embedded Reconfigurable Array Fabrics for Efficient Implementation of Image Compression Techniques
- AN EFFICIENT REFORMULATION BASED VLSI ARCHITECTURE FOR ADAPTIVE VITERBI DECODING IN WIRELESS APPLICATIONS
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- ISCAS 99, Florida USA, May 30th-June 2nd 1999, vol. 1, p. 80-83 1999 IEEE. Personal use of this material is However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or
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