Parcerisa, Joan-Manuel - Departament d'Arquitectura de Computadors, Universitat Polit�cnica de Catalunya

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Parcerisa, Joan-Manuel - Departament d'Arquitectura de Computadors, Universitat Polit�cnica de Catalunya

Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design
Improving Latency Tolerance of Multithreading through Joan-Manuel Parcerisa and Antonio Gonzlez
Improving Branch Prediction and Predicated Execution in Out-of-Order Eduardo Qui~nones
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and
In current superscalar processors, all floating-point resources are idle during the execution of integer programs.
This paper makes the case for the use of XOR-based placement functions for cache memories. It shows that these XOR-mapping
Reducing Wire Delay Penalty through Value Prediction Joan-Manuel Parcerisa and Antonio Gonzlez
Session S3B 978-1-4244-1970-8/08/$25.00 2008 IEEE October 22 25, 2008, Saratoga Springs, NY
Early Register Release for Out-of-Order Processors with Register Windows Eduardo Quiones
Clustered microarchitectures are an effective approach to reducing the penalties caused by wire delays inside a chip.
PREDICATED EXECUTION AND REGISTER WINDOWS FOR OUT-OF-ORDER PROCESSORS
The Latency Hiding Effectiveness of Decoupled Access/Execute Processors Joan-Manuel Parcerisa and Antonio Gonzlez
DESIGN OF CLUSTERED SUPERSCALAR MICROARCHITECTURES
The Synergy of Multithreading and Access/Execute Decoupling Joan-Manuel Parcerisa and Antonio Gonzlez
Selective Predicate Prediction for Out-of-Order Processors Eduardo Qui~nones
Memory Bank Predictors Stefan Bieschewski1