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Risset, Tanguy - Centre of Innovation in Telecommunications and Integration of Services & Département Informatique, INSA Lyon
Master Interface For On-Chip Hardware Accelerator Burst Communications
Long-Range Dependence and On-chip Processor Traffic
A reindexing based approach towards mapping of DAG with affine schedules onto parallel
Long-Range Dependence and On-chip Processor Traffic
A Generic Multi-Phase On-Chip Traffic Generation Environment Antoine Scherrer
Une Approche itrative pour l'allocation des tches sur rseaux rguliers
RenPar'18 / SympA'2008 / CFSE'6 Fribourg, Suisse, du 11 au 13 fvrier 2008
Hardware/Software Interface for Multi-Dimensional Processor Arrays Alain Darte
Andrew K. Chan and Cheng Peng May 21, 2008
UncorrectedProof High-Level Synthesis of Loops Using
Automatic Phase detection for Stochastic On-Chip Traffic During System on Chip (SoC) design, Network on Chip
