Nyathi, Jabulani - Department of Engineering and Design, Eastern Washington University

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Nyathi, Jabulani - Department of Engineering and Design, Eastern Washington University

The Vanishing Majority Gate Trading Power and Speed for Reliability
2004 4th IEEEConference on Nanotechnology On NanoelectronicArchitectural Challenges and Solutions
A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh
Logic Circuits Operating in Subthreshold Voltages Jabulani Nyathi and Brent Bero
A Hybrid Wave-PipelinedNetwork Router Jose G. Delgado-Frias Jabulani Nyathi
A High Performance, Low Area Overhead Carry Lookahead Adder
EVALUATION OF CPU UTILIZATION UNDER AHARDWARE-SOFTWARE PARTITIONED ENVIRONMENT (MIGRATING
A Distributed FIFO Scheme for on Chip Communication Ray Robert Rydberg III, Jabulani Nyathi, Jose G. Delgado-Frias
IEEE T-CAS-I (4923 = 4212 Revised): Special Issue on Nanoelectronic Circuits and Nanoarchitectures 1 Abstract--This paper will briefly review nanoelectronic
MULTIPLE CLOCK DOMAIN SYNCHRONIZATION FOR NETWORK ON CHIP ARCHITECTURES
Bulk CMOS Device Optimization for High-Speed and Ultra-Low Power Operations
An Efficient Key Update Scheme for Wireless Sensor Kamini Prajapati
The Second International Conference on Innovations in Information Technology (IIT'05) SUB-PICO JOULE SWITCHING
A HIGH PERFORMANCE, HYBRID WAVE-PIPELINED LINEAR FEEDBACK SHIFT REGISTER WITH SKEW TOLERANT CLOCKS
A Wave-Pipelined Router Architecture Using Ternary Associative Memory Jose G. Delgado-Frias* Jabulani Nyathi* Laxmi Bhuyant
A DYNAMIC CONTENT ADDRESSABLE MEMORY USING A 4-TRANSISTOR CELL
Self-timed Refreshing Approach for Dynamic Memories Jabulani Nyathi and Jos6 G. Delgado-F'rias
A Charge Recycling Differential Noise Immune Jabulani Nyathi, Valeriu Beiu, Suryanarayana Tatapudi, and David 3. Betowski
HIGH-PERFORMANCE PARALLEL ADDITION USING HYBRID WAVE-PIPELINING
Wave-Pipelining the Global Interconnect to Reduce the Associated Delays