Baniasadi, Amirali - Department of Electrical and Computer Engineering, University of Victoria

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Baniasadi, Amirali - Department of Electrical and Computer Engineering, University of Victoria

Low-Power Prediction Based Data Transfer Architecture
We study the energy efficiency benefits of bypass-ing trivial computations in high-performance proces-
We investigate instruction distribution methods for quad-cluster, dynamically-scheduled superscalar processors. We
We introduce asymmetric frequency clustering (AFC), a micro-architectural technique that reduces the dynamic power dis-
Using Lazy Instruction Prediction to Reduce Processor Wakeup Power Dissipation
SABA: a Zero Timing Overhead Power-Aware BTB for High-Performance Processors
Exploiting Program Cyclic Behavior to Reduce Memory Latency in Embedded Processors
Speculative Supplier Identification for Reducing Power of Interconnects in Snoopy Cache Coherence Protocols
We introduce Branch Predictor Prediction (BPP) as a power-aware branch prediction technique for high perfor-
Improving energy-efficiency in high-performance processors by bypassing trivial instructions
We describe the Slice Processor micro-architecture that imple-ments a generalized operation-based prefetching mechanism.
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Speculative trivialization point advancing in high-performance processors
Power-aware branch predictor update A. Baniasadi
A Power-Aware Alternative for the Perceptron Branch Predictor
Computational and Storage Power Optimizations for the O-GEHL Branch Predictor
Intel's XScale which has powered many multimedia applica-tions uses scoreboard to execute instructions. Scoreboard stalls the
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Designers have invested much effort in developing accurate branch predictors with short learning periods. Such techniques rely
We present a number of power-aware instruction front-end (fetch/decode) throttling methods for high-performance dynami-
We use value prediction to improve processor per-formance by speculating the trivializing operands in
Exploiting Task Temperature Profiling in Temperature-Aware Task Scheduling for
Branchless Cycle Prediction for Embedded Processors Kaveh Jokar Deris Amirali Baniasadi