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- A Critical-Path-Aware Partial Gating Approach for Test Power Reduction
- 896 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 5, MAY 2007 Local At-Speed Scan Enable Generation for
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- JOURNAL OF ELECTRONIC TESTING: Theory and Applications 20, 155168, 2004 c 2004 Kluwer Academic Publishers. Manufactured in The United States.
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- Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
- Supply Voltage Noise Aware ATPG for Transition Delay Faults Nisar Ahmed and Mohammad Tehranipoor
- A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects
- A New Hybrid FPGA with Nanoscale Clusters and CMOS Reza M.P. Rad, Mohammad Tehranipoor
- Timing-Based Delay Test for Screening Small Delay Nisar Ahmed, Mohammad Tehranipoor
- NnSP: Embedded Neural Networks Stream Hadi Esmaeilzadeh, Farhang Farzan, Neda Shahidi,
- Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression
- Mixed RL-Huffman Encoding for Power Reduction and Data Compression in Scan Test
- Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity
- An Efficient BIST Method For Testing of Embedded SRAMs M. H. Tehranipour, Z. Navabi, S. M. Fakhraie
- Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique
- Defect Tolerance for Nanoscale Crossbar-
- Partial Gating Optimization for Power Reduction During Test Application
- At-Speed Transition Fault Testing With Low Speed Scan Enable
- SCT: An Approach For Testing and Configuring Nanoscale Devices Reza M.P. Rad and Mohammad Tehranipoor
- Frequency Driven Repeater Insertion for Deep Submicron N. Ahmed, M. H. Tehranipour, D. Zhou, M. Nourani
- Low-Transition Test Pattern Generation for BIST-Based Applications
- A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks
- A Novel Pattern Generation Framework for Inducing Maximum Crosstalk Effects on Delay-Sensitive Paths
- Copyright 2008 American Scientific Publishers All rights reserved
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 6, JUNE 2005 719 Nine-Coded Compression Technique for Testing
- ITC Special Section 402 0740-7475/06/$20.00 2006 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
- Testing SoC Interconnects for Signal Integrity Using Boundary Scan M. H. Tehranipour, N. Ahmed, M. Nourani
- Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation* Jeremy Lee, Sumit Narayan, Mike Kapralos, and Mohammad Tehranipoor
- Enhanced Launch-Off-Capture Transition Fault Testing Nisar Ahmed1, Mohammad Tehranipoor2, C.P. Ravikumar1
- Securing Designs against Scan-Based Side-Channel Attacks
- Architecture of an Embedded Queue Management Engine for High-Speed Network Devices
- Layout-Aware Pattern Generation for Maximizing Supply Noise Effects on Critical Paths
- Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions
- Low Transition LFSR for BIST-Based Applications Mohammad Tehranipoor1, Mehrdad Nourani2, Nisar Ahmed3
- 800 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 of layers. For example, for three-layer routing, the circuit s38584