Polian, Ilia - Institut für Informatik, Albert-Ludwigs-Universität Freiburg

• Automatic Test Pattern Generation for Resistive Bridging Faults Piet Engelke1
• Identification of Critical Errors in Imaging Applications Ilia Polian Damian Nowroth Bernd Becker
• A Family of Logical Fault Models for Reversible Circuits Ilia Polian
• Exact Computation of Maximally Dominating Faults and Its Application to -Detection Tests
• A System for Calibration and Reliability Testing of MEMS Devices Under Mechanical Stress
• An Analysis Framework for Transient-Error Tolerance John P. Hayes Ilia Polian
• Simulating Open-Via Defects Stefan Spinner Jie Jiang Ilia Polian Piet Engelke Bernd Becker
• Efficient Bridging Fault Simulation of Sequential Circuits Based on Multi-Valued Logics
• Automatic Test Pattern Generation for Interconnect Open Defects Stefan Spinner
• On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
• Reducing ATE Cost in System-on-Chip Test Ilia Polian Bernd Becker
• Stop & Go BIST Ilia Polian Bernd Becker
• Low-Cost Hardening of Image Processing Applications Against Soft Errors Ilia Polian1,2
• Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting Jonathan Bradford Hartmut Delong Ilia Polian Bernd Becker
• Delta-IDDQ Testing of Resistive Short Defects Piet Engelke1
• Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST
• TIGUAN: Thread-parallel Integrated test pattern Generator Utilizing satisfiability ANalysis Alejandro Czutro
• Diagnose realistischer Defekte mit Hilfe des X-Fehlermodells Ilia Polian
• Selective Hardening of NanoPLA Circuits Ilia Polian
• Diagnosis of Realistic Defects Based on the X-Fault Model Ilia Polian
• Selective Hardening in Early Design Steps Christian G. Zoellin, Hans-Joachim Wunderlich
• Resistive Bridging Fault Simulation of Industrial Circuits Piet Engelke
• Power Droop Testing Ilia Polian1
• An Improved Technique for Reducing False Alarms Due to Soft Errors A significant fraction of soft errors in modern
• Functional Constraints vs. Test Compression in Scan-Based Delay Testing Ilia Polian1,2
• A Soft Error Emulation System for Logic Circuits Sandip Kundu
• Transient Fault Characterization in Dynamic Noisy Environments Ilia Polian1
• Resistive Bridge Fault Model Evolution From Conventional to Ultra Deep Submicron Technologies
• Evolutionary Optimization in Code-Based Test Compression Ilia Polian Alejandro Czutro Bernd Becker
• X-Masking During Logic BIST and Its Impact on Defect Coverage Yuyi Tang Hans-Joachim Wunderlich
• CONFIGURING MISR-BASED TWO-PATTERN BIST USING BOOLEAN SATISFIABILITY
• Sequential -Detection Criteria: Keep It Simple! Ilia Polian
• Publications of Ilia Polian Erdos-Nummer: 3 (through John Hayes and Frank Harary).
• A Simulator of Small-Delay Faults Caused by Resistive-Open Defects Alejandro Czutro
• A Study of Cognitive Resilience in a JPEG Compressor Damian Nowroth Ilia Polian Bernd Becker
• Extraction, Simulation and Test Generation for Interconnect Open Defects Based on Enhanced Aggressor-Victim Model
• Testing for Missing-Gate Faults in Reversible Circuits John P. Hayes1,2
• The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults
• SUPERB: Simulator Utilizing Parallel Evaluation of Resistive Bridges Piet Engelke1
• A System for Electro-Mechanical Reliability Testing of MEMS Devices Stefan Spinner
• Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time
• A Scalable BIST Architecture for Delay Faults Martin Keim Ilia Polian Harry Hengster Bernd Becker
• Modeling Feedback Bridging Faults With Non-Zero Resistance Ilia Polian Piet Engelke Michel Renovell Bernd Becker