De Micheli, Giovanni - Integrated Systems Centre, Ecole Polytechnique Fédérale de Lausanne

• pipesCompiler: A tool for instantiating application specific Networks on Chip
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 2053 Variability-Aware Design of Multilevel Logic
• REDUCTION OF REGISTER FILE DELAY DUE TO PROCESS VARIABILITY IN VLIW EMBEDDED PROCESSORS
• PANEL: PHYSICAL DESIGN AND SYNTHESIS: MERGE OR DIE !
• DaveFlloDavid Ku Claudionor N. Coelho. Jr. GiovanniDe Micheli Centerfor IntegratedSystems
• A new approach for dynamic reliability and power management of Integrated Systems, such as Systems on Chips (SoCs) and Networks
• Telescopic Units: A New Paradigm for Performance Optimization of VLSI Designs Lua Benini # GiovanniDe Micheli .
• IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 1, JANUARY 2010 1 Poly-Silicon Nanowire Transistors and Arrays
• A Simulation Methodology for Reliability Analysis in Multi-Core SoCs
• Networks on Chips 404 0740-7475/05/$20.00 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
• Self-Calibration Techniques 524 0740-7475/04/$20.00 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
• YO88S-0611 TPD R. K. Brayton and G. DeMicheli
• REDUCING POWER CONSUMPTION is a chal-lenge to system designers. Portable systems, such
• DECISION DIAGRAMS AND PASS TRANSISTOR LOGIC SYNTHESIS
• Stochastic Modeling and Analysis for Environmentally Powered Wireless Sensor Nodes
• 358 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 2, FEBRUARY 2006 A Pattern-Mining Method for High-Throughput
• Dynamic Scheduling and Synchronization Synthesis of Concurrent Digital Systems under System-Level Constraints
• An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service
• Mining gene sets for measuring similarities CHRISTINE NARDINI1
• DATA STRUCTURES FOR LOGIC OPTIMIZATION
• 964 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 8, AUGUST 2003 Complex Instruction and Software Library Mapping
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 4, APRIL 2007 391 Power and Reliability Management of SoCs
• Multicore thermal management using approximate explicit Model Predictive Control
• 242 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 2, FEBRUARY 2011 An Efficient Gate Library
• 554 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 4, DECEMBER 1998 Power Optimization of Core-Based Systems
• System-Level Power Optimization: Techniques and Tools
• Hardware/Software Co-Design GIOVANNI DE MICHELI, FELLOW, IEEE, AND RAJESH K. GUPTA, MEMBER, IEEE
• Finding Co-Clusters of Genes and Clinical Parameters Sungroh Yoon, Student Member, IEEE, Luca Benini, Senior Member, IEEE, and
• Adaptive Hard Disk Power Management on Personal Computers Yung-Hsiang Lu
• SUB-SYSTEMS 1960 1965 1970 1975 1980 1985 1990 1995 2000
• Packetization and routing analysis of on-chip multiprocessor networks
• Optimization of Reliability and Power Consumption in Systems on a Chip
• Implicit Methods for probabilistic modeling of Gene Regulatory Networks
• A Method for Calculating Hard QoS Guarantees for Networks-on-Chip
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 8, NO. 3, JUNE 2000 287 Glitch Power Minimization by Selective
• Cell-based logic optimization Giovanni De Micheli
• Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting
• A Multi-Path Routing Strategy with Guaranteed In-Order Packet Delivery and Fault-Tolerance for Networks on Chip
• Design Automation for Embedded Systems, 6, 89144 (2000) c 2000 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 7, JULY 2007 1297 Timing-Error-Tolerant Network-on-Chip
• Publications (as of March 24, 2011) 1. G. De Micheli, A. Sangiovanni-Vincentelli and P. Antognetti, Editors, Design Systems for VLSI Circuits
• 0018-9162/02/$17.00 2002 IEEE70 Computer Networks on Chips
• Bandwidth-Constrained Mapping of Cores onto NoC Architectures Srinivasan Murali, Giovanni De Micheli
• Dynamic Power Management for Portable Systems Tajana Simunic
• 840 IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 7, JULY 2001 Event-Driven Power Management
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 1, FEBRUARY 2001 15 Energy-Efficient Design of Battery-Powered
• Low power error resilient encoding for on-chip data buses Davide Bertozzi
• Address Bus Encoding Techniques for System-Level Power Optimization Luca Benini $ Giovanni De Micheli $ Enrico Macii Donatella Sciuto z Cristina Silvano
• Dynamic Power Management for non-stationary service requests Eui-Young Chung
• Designing Low-Power Circuits: Practical Recipes
• Transformation and synthesis of FSMs for low-power gated-clock implementation
• Hardware Synthesis from C/C++ Models Giovanni De Micheli
• Designing Application-Specific Networks on Chips with Floorplan Information Srinivasan Murali , Paolo Meloni
• 818 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 6, JUNE 2005 Error Control Schemes for On-Chip Communication
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 2, APRIL 2002 119 Power-Aware Operating Systems for
• Packetized On-Chip Interconnect Communication Analysis Terry Tao Ye
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 6, DECEMBER 2001 743 Synthesis of Hardware Models in C With Pointers
• Automatic for GeneralizedMapping Fundamental-Mode
• these protocols into a standard communication scheme. This scheme is then implemented in an interface architecture that
• 123IEEE TRANSACTIONSDN RELIABILITY. YOLo R-30. NO. 1. JUNE 1981 Computer-OrientedFormulation of Transition-Rate
• 220 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 3, MARCH 1998 Telescopic Units: A New Paradigm for
• Lookup Table Power Macro-models for Behavioral Library Components.
• 22 FALL 2010 IEEE SOLID-STATE CIRCUITS MAGAZINE 1943-0582/10/$26.002010IEEE Giovanni De Micheli
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 12, DECEMBER 2010 1987 SunFloor 3D: A Tool for Networks on Chip
• 364 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 57, NO. 5, MAY 2010 Comparative Analysis of NoCs for Two-Dimensional
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 1 Thermal Balancing Policy for Multiprocessor
• Computers and Mathematics with Applications 55 (2008) 938949 www.elsevier.com/locate/camwa
• Designing Micro-and Nanosystems for a Safer
• INTEGRATION, the VLSI journal 41 (2008) 340359 Invited paper
• Sensors & Transducers Journal, Vol.76, Issue 2, February 2007, pp.969-977 SSSeeennnsssooorrrsss &&& TTTrrraaannnsssddduuuccceeerrrsss
• BRINGING NOCS TO 65 NM VERY DEEP SUBMICRON PROCESS TECHNOLOGIES ARE IDEAL APPLICATION FIELDS FOR
• This Provisional PDF corresponds to the article as it appeared upon acceptance. Fully formatted PDF and full text (HTML) versions will be made available soon.
• Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and
• BioMed Central Page 1 of 12
• IEEE TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE, VOL. 11, NO. 4, JULY 2007 493 Communications
• Hindawi Publishing Corporation VLSI Design
• 0740-7475/05/$20.00 2005 IEEE Copublished by the IEEE CS and the IEEE CASS SeptemberOctober 2005 IT IS OUR PLEASURE TO INTRODUCE this special
• 1154 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 9, SEPTEMBER 2003 Application of Symbolic Computer Algebra in
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 2, FEBRUARY 2001 213 Resolution, Optimization, and Encoding of Pointer
• 1118 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 9, SEPTEMBER 2001 Synthesis of Power-Managed Sequential Components
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 6, DECEMBER 2001 783 Polynomial Circuit Models for Component Matching
• Synthesis of Low-Power Selectively-Clocked Systems from High-Level
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 4, APRIL 2000 459 A Multilevel Engine for Fast Power Simulation of
• Automatic selection of instruction op-codes of low-power core processors
• Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Synchronous
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 3, MARCH 1999 405 Reducing Switching Activity on Datapath
• 948 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 17, NO. 10, OCTOBER 1998 Iterative Remapping for Logic Circuits
• Guest Editor's Introduction: Hardware-Soft'Ware Codesign
• GIOVANNIDE MICHELI; StanfordUniversity and they are critical to the progress of the
• PLEASURE:A COMPUTEX PROGRAM FOR SIMPLJVMULTIPLE CONSlXAINED/UNCONSED FOLDING OF
• CRam THEORY AND APPLICAnONS. VOL 10. 299-3CW(1982) CHARAcrERIZAnON OF INTEGRA nON ALGORITHMS FOR
• PHYSICAL DESIGN TRADEOFFS IN POWER DISTRIBUTION NETWORKS FOR 3-D ICs
• Exploring Programming Model-driven QoS Support for NoC-based Platforms
• A Novel Multi-Working Electrode Potentiostat for Electrochemical Detection of Metabolites
• P450-Mediated Electrochemical Sensing of Drugs in Human Plasma for Personalized Therapy
• SB/RG/DR Talk Efficient method for generating minimal intervention sets in
• Process-Induced Skew Variation for Scaled 2-D and CH-1015, Switzerland
• Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement
• Memristive Devices Fabricated with Silicon Nanowire Schottky Barrier Transistors
• Power Consumption of Logic Circuits in Ambipolar Carbon Nanotube Technology
• A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control
• Characterization of Memristive Poly-Si Nanowires via Empirical Physical Modelling
• BIOINFORMATICS Vol. 25 ISMB 2009, pages i101i109
• Amperometric biosensor with nanostructured electrodes by using multi-walled carbon nanotubes for glucose detection in cell culture
• Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits
• Physically Clustered Forward Body Biasing for Variability Compensation in Nanometer CMOS design
• 3D Architecture and Replaceable Layers for Label-Free DNA Biochips
• Sensitivity Enhancement by Carbon Nanotubes: Applications to Stem Cell Cultures Monitoring
• Fabrication of Memristors with Poly-Crystalline Silicon Nanowires
• Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique
• NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs Ciprian Seiculescu , Srinivasan Murali
• Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis
• Optimal Multi-Processor SoC Thermal Simulation via Adaptive Differential Equation Solvers
• A Control Theory Approach for Thermal Balancing of MPSoC Francesco Zanini
• SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Ciprian Seiculescu , Srinivasan Murali
• Abstract The quest for technologies with superior device characteristics has showcased Carbon Nanotube Field Effect
• S.Carrara et al., Conference Proceedings of IEEE BioCAS 2008, Baltimore 20-22, November, 2008 978-1-4244-2879-3/08/$25.00 2008 IEEE 325
• Real-Time High-Sensitivity Impedance Measurement Interface for Tethered BLM Biosensor Arrays
• Modeling of Multiple Valued Gene Regulatory Networks Abhishek Garg, Luis Mendoza, Ioannis Xenarios and Giovanni DeMicheli
• A Simulation Model for Wireless Sensor Networks Based on TOSSIM Francisco J. Rincn1
• Application of FPGA Emulation to SoC Floorplan and Packaging Exploration
• Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays
• Reliability Support for On-Chip Memories Using Networks-on-Chip
• NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration Nicolas Genko , David Atienza
• A Novel Approach for Network on Chip Emulation N. Genko , D. Atienza
• Prediction and Analysis of Human microRNA Regulatory Modules Sungroh Yoon, Student Member, IEEE, and Giovanni De Micheli, Fellow, IEEE
• Self-Calibrating Networks-On-Chip Frederic Worm, Patrick Thiran, Giovanni de Micheli and Paolo Ienne
• Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
• Source Code Transformation based on Software Cost Analysis
• Luc Smria Koichi Sato Giovanni De Micheli lucs@azur.stanford.edu koichi@azur.stanford.edu nanni@galileo.stanford.edu
• Dynamic Power Management of Laptop Hard Disk Tajana Simunic, Luca Benini
• Event-Driven Power Management of Portable Systems
• Glitch Power Minimization by Gate Freezing L. Benini3 G. De Micheli A. Maciiz E. Maciiz M. Poncinoz R. Scarsiz
• Methods for performing component matching by expressing an arithmetic specification and a bit-level
• Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding
• Reducing Coding Style E ects in High-Level Speci cations Claudionor Jos e Nunes Coelho Jr. Giovanni De Micheli
• Optimization of Combinational Logic Circuits Based on Compatible Gates *
• OP11MALENCODING OF CONTROL LOGIC GiovanniDeMicheli
• NKW ALCOHI-nIY:\ (O'OKT1~11NG"NAJ.Y~':\ or I.AHGK CIKCU~ G. De Micbeli. A. Sanllovannl-Yincenlclti. A. R. Nc.ton
• Designing Routing and Message-Dependent Deadlock Free Networks on Chips
• Networks on chips: A new paradigm for component-based MPSoC design
• RECEIVED VECTOR BUFFER REGISTER SYNDROME CALCULATION CIRCUIT
• Chapter #16 Energy-efficient system-level design
• Applications Kernel Power Management
• Giovanni DeMicheli Technical Report No. CSL-TR-92-551
• Efficient Computationof ExactandSimplified Observability Don't careSetsfor Multiple-Level CombinationalNetworks
• DECOMPOSITIONTECHNIQUES FOR LARGE SCALE CIRCUIT ANAL YSISAND SIMULA TI 0 N
• Luc Smria Giovanni De Micheli lucs@azur.stanford.edu nanni@galileo.stanford.edu
• Dynamic Power Management of Electronic Circuits and Systems Luca Benini GiovanniDe Micheli
• JeromeFron Jerry Chih-YuanYang MaurizioDamiani GiovanniDe Micheli Centerfor Inte~ratedSystems
• ClaudionorN. Coelho,Jr. Giovanni De MicheliRajesh K. Gupta ComputerSystemsLaboratory
• Giovanni De Micheli ComputerSystemsLaboratory
• services and opportunities in the 21st century
• COMPUTER SYSTEMS LABORATORY STANFORD UNIVERSITY . STANFORD, CA 943054055, . .
• SUBNANOSECOND ARITHMETIC Second Report
• A Non-Invasive Approach for Molecular Characterization of Glioblastoma Multiforme: Magnetic Resonance Imaging Correlation with cDNA Microarray Expression Profiles
• Multi-Processor Operating System Emulation Framework with Thermal Feedback for Systems-on-Chip
• System-Level Design for Nano-Electronics David Atienza1,2
• Power Distribution Paths in 3-D ICs Vasilis F. Pavlidis Giovanni De Micheli
• On-Going Research on Address Bus Encoding for Low Power: A Status Report L. Benjni. G. De Midleli s c. Silvaoo.D. Sciuto SE.Macii. M . Poncino s. Quer
• System-level Dynamic Power Management G. De Micheli tL. Benini A. Bogliolo
• David C. Ku andGiovanniDeMicheli Centerfor Integrated Systems,Stanford University,Stanford, CA 94305-4055,USA
• HW-SW Emulation Framework for Temperature-Aware Design in MPSoCs
• In Proceedings of the 8th International Workshop on Field Programmable Logic and Applications (FPL98),
• Robust System Design with Uncertain Information Giovanni De Micheli
• Synchronization and Power Integrity Issues in 3-D ICs Vasilis F. Pavlidis, Hu Xu, Ioannis Tsioutsios, and Giovanni De Micheli
• Dyndc Power Management of Electronic Systems LucaBeniti Alessmdro Bogtiolo GiovanniDe Mchefit
• Computer-aided evaluation of protein expression in pathological tissue images Elisa Ficarra, Enrico Macii
• Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips
• Giovanni De Micheli and Mauro Santomauro* Thispaper presentsa new approach to optimal topological
• A METHOD FOR EXTRACTING IMAGING CORRELATIONS WITH ALTERATIONS IN GLOBAL GENE EXPRESSION
• IMPLEMENTATION OF AN AUTOMATED ECG-BASED DIAGNOSIS ALGORITHM FOR A WIRELESS BODY SENSOR PLATFORM
• Synthesis and Optimization of Digital Circuits Giovanni De Micheli
• A Complete Network-On-Chip Emulation Framework N. Genko , D. Atienza
• Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique
• Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors
• translation synthesis &
• An Adaptive Low-power Transmission Scheme for On-chip Networks
• Abstract--Clustering has been one of the most popular techniques to analyze gene expression data. The biclustering
• Derivationof Don't careConditions Giovanni De MicheliMaurizio Damiani
• Automatic Instruction Set Extension and Utilization for Embedded Processors Armita Peymandoust, Laura Pozzi
• Multicore Thermal Management with Model Predictive Francesco Zanini
• 1284 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 11, NOVEMBER 2002 Dynamic Frequency Scaling With Buffer Insertion
• Biosensors and Bioelectronics 24 (2009) 34253429 Contents lists available at ScienceDirect
• New probe immobilizations by Lipoate-Diethalonamines or Ethylene-Glycol molecules for Capacitance DNA Chip
• 126 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 1, JANUARY 2005 A Robust Self-Calibrating Transmission Scheme for
• Y0886-0998 RRS G. DeMicheli and A. Ruehli
• BIOINFORMATICS ORIGINAL PAPER Vol. 24 no. 17 2008, pages 19171925
• Computer Systems Laboratory Technical Report Report No. CSL-TR-97-739 Hardware Software Co-Design of Run-Time Schedulers for
• Heterogeneous wireless network management Wajahat Qadeer1
• Improving the Fault Tolerance of Nanometric PLA Designs Federico Angiolini1
• Designing Robust Systems with Uncertain Information Giovanni De Micheli
• Dynamical Spot Queries to Improve Specificity in P450s based Multi-Drugs Monitoring
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 9, SEPTEMBER 2002 1051 Value-Sensitive Automatic Code Specialization for
• A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework
• David C. Ku Dave Fila GiovanniDe Micheli Centerfor Integrated Systems
• Enhanced pClustering and Its Applications to Gene Expression Data Sungroh Yoon
• Characterization-Free Behavioral Power Modeling Alessandro Bogliolo Luca Beniniy
• L. Beninit D. Guan* G. De MichelitD. Ku. t CSt -Stanford University
• A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control
• Routing Aware Switch Hardware Customization for Networks on Chips
• Abstract--Bio-detection specially dedicated to distributed diagnostics is emerging as a quite important application for Nano-
• Copyright 2006 American Scientific Publishers All rights reserved
• The Role of Don't care Conditions in SynchronousLogic Optimization*
• Conflict Compatibility Coloring Covering
• Fabrication and Characterization of Vertically Stacked Gate-AIl-Around Si Nanowire FET Arrays
• Synthesisof High-PerfonnanceDigital Circuits: Logic Transformations for Cycle-Time Reduction of Synchronous Circuits
• pipes Lite: A Synthesis Oriented Design Library For Networks on Chips Stergios Stergiou1
• Networks on Chips: from Research to Products
• Managing heterogeneous wireless environments via Hotspot servers T. Simunic"2, W. Qadeer1, and G. De Micheli'
• Generalized Matching: a new approach to concurrent logic optimization and library binding
• Timed Supersetting and the Synthesis of Large Telescopic Units L. Benini G. De Micheli A. Lioy z E. Macii z G. Odasso z M. Poncino z
• Carbon Nanotubes-Based Electrochemical Sensing for Cell Culture Monitoring
• 1. Introduction ith the growing complexity in consumer embed-
• Biosensors and Bioelectronics 26 (2011) 39143919 Contents lists available at ScienceDirect
• Copyright Stanford University, Universit di Bologna, STMicroelectronics 2001 ST Journal of System Research
• Author's personal copy Surface Science Letters
• Temperature Sensor Placement in Thermal Management Systems for MPSoCs
• A GATE-LEVEL POWER SIMULATOR A WORLD WIDE WEB APPLICATION
• A Survey of Boolean Matching Techniques for Library Binding
• INTERNATIONAL JOURNAL OF CIRctJlT THEORY AND APPLICATIONS, YOLo 16,347-369 (1981) COMPUTER-AIDED DESIGN AND OPTIMIZATION
• Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework
• Luca Benini and Giovanni De Micheli Stanford University.
• Dise~no de redes en chip de proposito especifico con informacion de rutado fisico
• Optimal synthesis of gated clocks for low-power Finite-State Machines
• STAGE1STAGE2 STAGE1STAGE2
• NoC Design and Implementation in 65nm Technology
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 8, AUGUST 2007 869 Synthesis of Predictable Networks-on-Chip-Based
• Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures
• SPECTRAL TECHNIQUES FOR TECHNOLOGY MAPPING
• Synthesis of regular computational fabrics with ambipolar CNTFET technology
• AlessandroBedarida.Silvia ErcolaniandGiovanniDe Micheli Centerfor IntegratedSystems
• Int. J. Embedded Systems, Vol. 3, No. 4, 2008 209 On-chip implementation of multiprocessor networks
• Online Convex Optimization-Based Algorithm for Thermal Management of MPSoCs
• L. Semena,!(. Salo, G. De Micheli Memory Representationand Hardware Synthesisof C Codewith
• This article was published in an Elsevier journal. The attached copy is furnished to the author for non-commercial research and
• 240 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 3, MARCH 1997 Specification and Analysis of Timing
• Networks on Chips 434 0740-7475/05/$20.00 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
• HardwareC -A Language for Hardware Design Version 2.0
• An Efficient Method for Dynamic Analysis of Gene Regulatory Networks
• Computational Identification of MicroRNAs and Their Targets
• Synthesis From Mixed Speci cations Vincent J. Mooney III
• 1994 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 56, NO. 9, SEPTEMBER 2009 Processor Speed Control With Thermal Constraints
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 6, JUNE 2009 777 Keynote Paper
• Reliability-Aware Design for Nanometer-Scale Devices David Atienza1,2
• Quantitative Comparison of Power Management Algorithms Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic,
• Synthesis of Networks on Chips for 3D Systems on Chips Srinivasan Murali , Ciprian Seiculescu , Luca Benini
• An Application-Specific Design Methodology for STbus Crossbar Generation Srinivasan Murali, Giovanni De Micheli
• Nano-Tera.CH: Nano-technologies for Tera-scale Problems Giovanni De Micheli
• Programmable Locgic Circuits Based on Ambipolar CNFET M. Haykel Ben Jamaa1
• Optimal Frequencies for Inductive Powering of Fully Implantable Biosensors for Chronic and Elderly
• m1: {v1,OR2} m2: {v2,AND2}
• LOGIC SYNTHESIS FOR LOW POWER Luca Benini
• A Stochastic Perturbative Approach to Design a Defect-Aware Thresholder in the Sense Amplifier of Crossbar Memories
• Elisa Ficarra1 , Giovanni De Micheli1
• Quantum Dots and Wires to improve Enzymes-Based Electrochemical Bio-sensing
• Discovering Coherent Biclusters from Gene Expression Data Using
• 10 IEEE CIRCUITS AND SYSTEMS MAGAZINE 1531-636X/06/$20.002006 IEEE THIRD QUARTER 2006 Introduction
• A Methodology for Mapping Multiple Use-Cases onto Networks on Chips Srinivasan Murali
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 7, JULY 2007 1283 An Application-Specific Design Methodology for
• Mapping and Configuration Methods for Multi-Use-Case Networks on Chips Srinivasan Murali
• Compiler-Driven Leakage Energy Reduction in Banked Register Files
• Automatic Source Code Specialization for Energy Reduction
• IEEE SOLID-STATE CIRCUITS MAGAZINE SUMMER 2010 87 presentation the following day will be
• Low Power Embedded Software Optimization using Symbolic Algebra Armita Peymandoust
• r = p + a' s = r + b' t = ac + ad + bc + bd + e
• Prospects for logic-on-a-wire K.E. Moselund *, D. Bouvet, M.H. Ben Jamaa, D. Atienza, Y. Leblebici,
• R. Scarsi *M. PoncinofE. Macii~L. Benini # G. De Micheli # # Stanford University
• NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
• This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE ELECTRON DEVICE LETTERS 1
• Delivered by Ingenta to: IP : 93.32.32.85
• 978-1-4244-9350-0/11/$26.00 2011 IEEE 1523 2011 4th International Conference on Biomedical Engineering and Informatics (BMEI)
• IEEE SENSORS JOURNAL, VOL. 11, NO. 7, JULY 2011 1573 Energy Harvesting and Remote Powering
• J.L. Ayala et al. (Eds.): PATMOS 2011, LNCS 6951, pp. 267277, 2011. Springer-Verlag Berlin Heidelberg 2011
• IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 10, NO. 4, JULY 2011 891 Polysilicon Nanowire Transistors and Arrays
• 182 978-4-86348-164-0 2011 Symposium on VLSI Technology Digest of Technical Papers 10A-3 (Invited)
• BioNanoSci. (2011) 1:13 DOI 10.1007/s12668-011-0002-9
• An Integrated Platform for Advanced Diagnostics Giovanni De Micheli, S. Sara Ghoreishizadeh, Cristina Boero, Francesco Valgimigliand Sandro Carrara
• Ambipolar silicon nanowire FETs with stenciled-deposited metal gate Davide Sacchetto
• 242 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 2, FEBRUARY 2011 An Efficient Gate Library
• Design and Analysis of NoCs for Low-Power 2D and 3D SoCs
• Biosensors and Bioelectronics 26 (2011) 39143919 Contents lists available at ScienceDirect
• Alternative Design Methodologies for the Next Generation Logic Switch
• Modeling of Printed Spiral Inductors for Remote Powering of Implantable Biosensors
• Example-based Support Vector Machine for Drug Concentration Analysis
• A DRAM Centric NoC Architecture and Topology Design Approach Ciprian Seiculescu , Srinivasan Murali
• Reliable Circuits Design with Nanowire Arrays M. Haykel Ben Jamaa and Giovanni De Micheli
• Sensors and Actuators B 160 (2011) 327333 Contents lists available at ScienceDirect
• 9.1 Introduction Today, many integrated circuits contain several processor cores, memories, hard-
• AMBIPOLAR SI NANOWIRE FIELD EFFECT TRANSISTORS FOR LOW CURRENT AND TEMPERATURE SENSING
• Skew Variability in 3-D ICs with Multiple Clock Domains Hu Xu, Vasilis F. Pavlidis, and Giovanni De Micheli
• Thermal-Aware System-Level Modeling and Management for Multi-Processor Systems-on-Chip
• P450-Based Nano-Bio-Sensors for Personalized Medicine
• Top-down fabrication of very-high density vertically stacked silicon nanowire arrays with low temperature budget
• CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips
• Advances, Challenges and Opportunities in 3D CMOS Sequential Integration , M. Vinet1
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• Delivered by Ingenta to: Ecole polytechnique federale de Lausanne
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