- Limits and Opportunities for Designing Manycore Processor-to-Memory Networks using Monolithic Silicon Photonics
- Appears in 35th IEEE/ACM International Symposium on Computer Architecture (ISCA), Beijing, China, June 2008. Globally-Synchronized Frames for
- In IEEE Int'l Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, March 2006. Accelerating Architectural Exploration Using Canonical Instruction Segments
- Replacing Global Wires with an On-Chip Network: A Power Analysis
- "!$#%'&(0)11!3245 !6879)1!$@BA 1CDE!$@FE#GH5I5#PFQ79R0)TSGU5VXWY5
- Appears in, The 31st Annual International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004 The Vector-Thread Architecture
- Appears in Kool Chips Workshop, 33rd International Symposium on Microarchitecture, Monterey, CA, December 2000 Highly-Associative Caches for Low-Power Processors
- Appears in Workshop on Complexity-Effective Design, 27th ISCA, Vancouver, Canada, June 2000 SyCHOSys: Compiled Energy-Performance Cycle Simulation
- Mondrix: Memory Isolation for Linux using Mondriaan Memory Protection
- AXCIS: Rapid Processor Architectural Exploration using Canonical Instruction Segments
- Tessellation: Space-Time Partitioning in a Manycore Client OS Rose Liu, Kevin Klues, Sarah Bird, Steven Hofmeyr
- Appears in First USENIX Workshop on Hot Topics in Parallelism (HotPar-09), Berkeley, CA, March 2009 Lithe: Enabling Efficient Composition of Parallel Libraries
- List of Figures III List of Tables V
- Intelligent RAM (IRAM): the Industrial Setting, Applications, and Architectures David Patterson, Krste Asanovic, Aaron Brown, Richard Fromm,
- Vector Microprocessors Krste Asanovic
- EProf: An Energy Profiler for the iPAQ Kelly Koskelin
- The Case for Malleable Stream Architectures Christopher Batten 1, Hidetaka Aoki 2, Krste Asanovic 3
- Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection
- ) 0 1 2 3 4 1 5 6 7 8 9 @A B 3 C 1 7 6 D 7 0 E 5 6
- Heads and Tails: A Variable-Length Instruction Format Supporting Parallel Fetch and Decode
- Implementing the Scale Vector-Thread RONNY KRASHINSKY, CHRISTOPHER BATTEN, and KRSTE ASANOVI C
- Way Memoization to Reduce Fetch Energy in Instruction Caches Albert Ma, Michael Zhang, and Krste Asanovic
- SEJITS: Getting Productivity and Performance With Selective Embedded JIT Specialization
- An FPGA Host-Multithreaded Functional Model for SPARC v8 Zhangxi Tan
- PARALLEL NEURAL NETWORK TRAINING ON MULTISPERT
- RAMP: RESEARCH ACCELERATOR FOR MULTIPLE PROCESSORS
- Improving Energy Efficiency and Reducing Code Size with RISC-V Compressed
- Abstract Modern performance-oriented ISAs, such as RISC and VLIW, only expose to software features that impact the critical path through computation. Pipelined
- Appears in the Proceedings of the 3rd International Symposium on Networks-on-Chip (NOCS-3), May 2009 Silicon-Photonic Clos Networks for Global On-Chip Communication
- Introduction Nowadays, portable devices such as laptop and notebook computers are very popular.
- Sieve: An XML-Based Structural Verilog Rules Submitted to the Department of Electrical Engineering and Computer
- Computer Science and Artificial Intelligence Laboratory Technical Report
- A Fast Kohonen Net Implementation for Krste Asanovi c
- 0018-9162/96/$5.00 1996 IEEE March 1996 79 any algorithms used in human-machine interface applica-
- Microprocessor Energy Characterization and Optimization through Fast, Accurate, and Flexible Simulation
- Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
- Manycore Processor Networks with Monolithic Integrated CMOS Photonics
- REAL-TIME MUSICAL APPLICATIONS ON AN EXPERIMENTAL OPERATING SYSTEM FOR MULTI-CORE PROCESSORS
- Parallelizing the Web Browser Christopher Grant Jones, Rose Liu, Leo Meyerovich, Krste Asanovic, Rastislav Bodk
- Efficient VLSI Implementations of Vector-Thread Architectures by Yunsup Lee
