Lee, Hsien-Hsin "Sean" - School of Electrical and Computer Engineering, Georgia Institute of Technology

• General Overview of an Adaptive Dynamic Extensible Processor Hamid Noori, Kazuaki Murakami and Koji Inoue
• Kicking the Tires of Software Transactional Memory: Why the Going Gets Tough
• SHARK: Architectural Support for Autonomic Protection Against Stealth by Rootkit ExploitsAgainst Stealth by Rootkit Exploits
• A Practical Approach for `Zero' Downtime in an Operational Information Ada Gavrilovska, Karsten Schwan, Van Oleson
• Towards the Issues in Architectural Support for Protection of Software Weidong Shi
• "Anv clond con hnva thA frni tc Response to "Computers, Complexity, and Controversy"
• Virtual Exclusion: An Architectural Approach to Reducing Leakage Energy in Caches for Multiprocessor Systems
• Using an FPGA as a Prototyping Platform for Multi-core Processor Applications Christopher R. Clark, Ripal Nathuji, Hsien-Hsin S. Lee
• RETROSPECTIVE: Implementing PreciseInterrupts in Pipelined Processors
• Research Experience for Undergraduates (REU) Supplemental Funding from the National Science Foundation (NSF)
• ECE2030A Fall 2008 Prof. H.-H. S. Lee Georgia Tech Page 1 of 6
• This research was supported by NSF Information Technology Research Contract, CCR 022-0259.
• COMPASS: A Programmable Data Prefetcher Using Idle GPU Shaders
• ThreadMarks: A Framework for Input-Aware Prediction of Parallel Application Behavior
• Cache Memories ALAN JAY SMITH
• The 19th Annual International Symposium on Computer Architecture pp. 124 -134, May 19 -21, 1992, Gold Coast, Australia.
• FALL 2008 President's Undergraduate Research Awards (PURA) School Student Name
• ECE3055 Prof. H.-H. S. Lee Georgia Tech Page 1 of 6
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 7, JULY 2006 1289 Profile-Guided Microarchitectural Floor Planning
• Testing Circuit-Partitioned 3D IC Designs
• Design and Analysis of 3D-MAPS: A Many-core 3D Processor with Stacked Memory
• Towards the Issues in Architectural Support for Protection of Software Weidong Shi
• Cache Coherence Support for Non-Shared Bus Architecture on Heterogeneous MPSoCs
• J. Parallel Distrib. Comput. 70 (2010) 443457 Contents lists available at ScienceDirect
• PROPHET: Goal-Oriented Provisioning for Highly Tunable Multicore Processors in Cloud Computing
• Spring 2008 President's Undergraduate Research Awards (PURA) Student Name Major Mentor Name
• Phase based adaptive branch predictor: Seeing the forest for the trees
• Technical Note REEVALUATING AMDAHL'S LAW
• Helper Transactions: Enabling Thread-Level Speculation via A Transactional Memory System
• SECURITY REFRESH: PROTECTING PHASE-CHANGE MEMORY AGAINST
• Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multicore
• An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth
• Architectural Evaluation of 3D Stacked RRAM Caches Dean L. Lewis Hsien-Hsin S. Lee
• Test Challenges for 3D Integrated Circuits
• Way Guard: A Segmented Counting Bloom Filter Approach to Reducing Energy for Set-Associative Caches
• Thermal Optimization in Multi-Granularity Multi-Core Floorplanning
• SHARK: Architectural Support for Autonomic Protection Against Stealth by Rootkit Exploits
• POD: A 3D-INTEGRATED BROAD-PURPOSE ACCELERATION LAYER
• Improving TLB Energy for Java Applications Chinnakrishnan S. Ballapuram
• Graphics Hardware (2008) David Luebke and John D. Owens (Editors)
• Total Recall: A Debugging Framework Ahmad Sharif and Hsien
• Adaptive Transaction Scheduling for Transactional Memory Systems
• Exploiting Access Semantics and Program Behavior to Reduce Snoop Power in Chip Multiprocessors
• Bicephaly: Maximizing Bandwidth by Duplexing Power and Data
• A Scan-Island Based Design Enabling Pre-bond Testability in Die-Stacked Microprocessors
• Hierarchical Means: Single Number Benchmarking with Workload Cluster Analysis
• POD: A Parallel-On-Die Architecture Dong Hyuk Woo1
• An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems
• Secure Processing On-Chip Hsien-Hsin S. Lee Santosh Pande
• 38 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 1, JANUARY 2007 Multiobjective Microarchitectural Floorplanning
• Reducing Cache Pollution via Dynamic Data Prefetch Filtering
• Authentication Control Point and Its Implications For Secure Processor Design
• DRAM Decay: Using Decay Counters to Reduce Energy Consumption in DRAMs
• Constructing a Non-Linear Model with Neural Networks for Workload Characterization
• Reducing Energy of Virtual Cache Synonym Lookup using Bloom Filters
• Entropy-Based Low Power Data TLB Design Chinnakrishnan Ballapuram
• J. Parallel Distrib. Comput. 66 (2006) 11161128 www.elsevier.com/locate/jpdc
• A Low-cost Memory Remapping Scheme for Address Bus Protection Lan Gao Jun Yang Marek Chrobak Youtao Zhang* San Nguyen Hsien-Hsin S. Lee
• Efficient System-on-Chip Energy Management with a Segmented Bloom Filter
• Memory-centric Security Architecture Weidong Shi Chenghuai Lu Hsien-Hsin S. Lee
• Synonymous Address Compaction for Energy Reduction in Data TLB
• Attacks and Risk Analysis for Hardware Supported Software Copy Protection Systems
• Hardware Assisted Control Flow Obfuscation for Embedded Processors
• Supporting Cache Coherence in Heterogeneous Multiprocessor Systems
• In Proceedings of the 32nd International Conference on Parallel Processing, Kaohsiung, Taiwan, October, 2003. A Hardware-based Cache Pollution Filtering Mechanism
• In the Workshop on Complexity-Effective Design in conjunction with ISCA-30, San Diego, CA, 2003. The Elusive Metric for Low-Power Architecture Research
• SEMANTICS-ORIENTED LOW POWER ARCHITECTURE
• INTEGRATION AND EVALUATION OF CACHE COHERENCE PROTOCOLS FOR MULTIPROCESSOR
• SUBVERTING LINUX ON-THE-FLY USING HARDWARE VIRTUALIZATION TECHNOLOGY
• ARCHITECTURAL SUPPORT FOR AUTONOMIC PROTECTION AGAINST STEALTH BY ROOTKIT
• WATERMARKING FPGA BITSTREAM FOR IP Presented to
• Summer 2011 President's Undergraduate Research Award (PURA) Award School Student Name Student Major
• POD: A Parallel-On-Die Architecture Dong Hyuk Woo1
• ECE 2030 --Introduction to Computer Engineering Section A, Fall 2008
• Supplement to Logic and Computer
• Supplement to Logic and Computer
• Mixed Logic Introduction
• ECE3055 Fall 2006 Prof. H.-H. S. Lee Georgia Tech Page 1 of 5
• Instruction Sets and Beyond: Computers, Complexity,
• Improving the Accuracy of Dynamic Branch Prediction Using Branch Correlation
• R. M. Tomasulo An Efficient Algorithm for Exploiting
• Mayan Moudgill IBM TJ. Watson Research
• Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor
• The Stanford Dash Multiprocessor
• Shared Memory Consistency Models: A Tutorial Sarita V. Advey
• Four Easy Ways to Register Online: http://vlsisoc2007.dlpe.gatech.edu
• A Dynamically Reconfigurable Virtual Instrument Gerd Van den Branden 1
• A Preliminary Evaluation of Timing-Speculative Instruction Collapsing Toshinori Sato Akihiro Chiyonobu
• Instruction-Window Power Reduction Using Data Dependence Metric
• Call For Papers WISA-07 Second Workshop on Introspective Architectures
• Information for Faculty/Staff/Mentors Funding for Undergraduate Research
• Materials, Supplies, & Travel Grants for Undergraduate Research Fall 2010, Spring 2011 or Summer 2011
• Poster Evaluation Poster Number
• Georgia Tech's Research Option
• Information provided by Dr. Lisa Rosenstein, Communications Specialist, MSE and CEE Scientific Poster Guidelines and Suggestions
• Research Option --Proposal Content and Requirements Each student is required to prepare (and have approved by their unit) a proposal outlining the
• Tips and Suggestions for Faculty Mentors of Research Option Students semester of research
• Guidelines for Applying for Georgia Tech Presidents Undergraduate Research Awards (PURAs)
• Guidelines for Applying for Georgia Tech Presidents Undergraduate Research Awards (PURAs)
• President's Undergraduate Research Award (PURA) Information Travel Awards
• Summer 2010 President's Undergraduate Research Awards School Student Name
• President's Undergraduate Research Awards (PURA) Spring 2010 School Student Name
• President's Undergraduate Research Awards (PURA) Fall 2009 School Student Name
• President's Undergraduate Research Awards (PURA) Summer 2009 School Student Name
• President's Undergraduate Research Awards (PURA) Spring 2009 School Student Name
• 562 IEEE TRANSACTIONS ON COMPUTERS, VOL. 31,NO. 5, MAY 1988 Implementing Precise Interrupts in Pipelined
• ECE3055 Summer 2005 Prof. H.-H. S. Lee Georgia Tech Page 1 of 5
• Security Refresh: Prevent Malicious Wear-out and Increase Durability for Phase-Change Memory with Dynamically
• A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
• More controversy about "Computers, Complexity, and Controversy" David Patterson and John Hennessy's
• Fall 2010 President's Undergraduate Research Awards Award School Student Name Student Major Mentor Name Paper Title Funding Type
• The Itanium processor is the first implementation of the IA-64 instruction set
• High Performance Non-blocking Switch Design in 3D Die-Stacking
• Journal of Instruction-Level Parallelism 13 (2011) 1-17 Submitted 3/10; published 1/11 Data Prefetching by Exploiting Global and Local Access
• President's UndergraduatePresident's Undergraduate Research AwardResearch Award --InformationInformation
• Journal of Instruction-Level Parallelism 3 (2001) Improving Bandwidth Utilization using Eager Writeback
• UROP Research Coordinators Research Coordinator Email
• Design and Test of 3D-MAPS, a 3D Die-Stack Many-Core Dean L. Lewis, Michael B. Healy, Mohammad M. Hossain, Tzu-Wei Lin, Mohit Pathak
• The MIPS programs we have seen to this point involve a sequence of instructions that are uncondition-ally executed. In other words every instruction is executed and all instructions are executed in the order
• Cellule: Lightweight Execution Environment for Accelerator-based Systems
• The Research Option is: n a demanding research program designed for students
• Analyzing Performance Vulnerability due to Resource Denial-of-Service Attack on Chip Multiprocessors
• Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs
• Architectural Support for Protecting Memory Integrity and Confidentiality
• Summer 2006 President's Undergraduate Research Awards (PURA) Page 1 of 3 of Award Advisor Project Title
• Service Morphing: Integrated System-and Application-Level Service Adaptation in Autonomic Systems
• ECE 4100/6100 Advanced Computer Architecture
• WISA06 Final Program Sunday Feb. 12th 2006
• Protecting Human Subjects in Research:Protecting Human Subjects in Research: Actions and ReactionsActions and Reactions
• ECE3055 Summer 2005 Prof. H.-H. S. Lee Georgia Tech Page 1 of 5
• Register renaming is a technique to remove false data dependencies--write after
• Memory technology evolution: an overview of system memory technologies
• Undergraduate Research at GTUndergraduate Research at GT http://www.undergradresearch.gatech.edu
• Matching Test Cases for Effective Fault Localization George K. Baah, Andy Podgurski, and Mary Jean Harrold
• ECE 8833 Fall 2009 Polymorphic and Many-Core Computer Architecture
• Extending Amdahl's Law for Energy-Efficient
• HSIEN-HSIN SEAN LEE ASSOCIATE PROFESSOR
• Predicate-Aware Scheduling: A Technique for Reducing Resource Constraints
• Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling
• Frequently Asked Questions 1. How do I get started?
• SoftCache Architecture Presented to
• ECE3055 Fall 2006 Prof. H.-H. S. Lee Georgia Tech Page 1 of 9
• A Unified Methodology for Power Supply Noise Reduction in Modern Microarchitecture Design
• Today, the heterogeneous demands of embedded-systems applications naturally
• MICROARCHITECTURAL TECHNIQUES TO REDUCE ENERGY CONSUMPTION IN THE
• DLL-Conscious Instruction Fetch Optimization for SMT Processors
• IdlePower: Application-Aware Management of Processor Idle States Hrishikesh Amur Ripal Nathuji Mrinmoy Ghosh
• Instruction Set Architecture 1 Instruction Set
• Adaptable Mirroring in Cluster Servers Ada Gavrilovska, Karsten Schwan, Van Oleson
• A case for coordinated resource management in heterogeneous multicore Priyanka Tembey
• INSTRUCTION ISSUE LOGIC FOR HIGH-PERFORMANCE, INTERRUPTABLE P1PELINED PROCESSORS
• PreDatA -Preparatory Data Analytics on Peta-Scale Fang Zheng1
• Fast, Lightweight Virtual Machine Checkpointing Michael H. Sun Douglas M. Blough
• Dominant Variance Characterization Tushar Kumar
• Testing Circuit-Partitioned 3D IC Designs Dean L. Lewis Hsien-Hsin S. Lee
• Test Strategies for 3D Die-Stacked Integrated Circuits Dean L. Lewis
• Mobile applications constantly demand additional memory, and traditional
• Optimizing Katsevich Image Reconstruction Algorithm on Multicore Processors
• Pre-bond Testable Low-Power Clock Tree Design for 3D Stacked ICs
• System Impact of 3D Processor-Memory Interconnect: A Limit Study
• ECE3055 Summer 2005 Prof. H.-H. S. Lee Georgia Tech Page 1 of 6
• An Integrated Framework for Dependable and Revivable Architectures Using Multicore Processors
• Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching Eric Rotenberg
• Towards Optimal Power Management: Estimation of Performance Degradation due to DVFS on Modern
• Exploring the Design Space of Greedy Link Scheduling Algorithms for Wireless Multihop
• Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems
• High Performance Non-blocking Switch Design in 3D Die-Stacking Technology
• An Introduction to DRAM Dynamic random access memory (DRAM) integrated circuits (ICs) have
• Initial Observations of Hardware/Software Co-Simulation using FPGA in Architecture Research
• Efficient Indexing Structure for Scalable Processing of Spatial Alarms
• 330272-1732/04/$20.00 2004 IEEE Published by the IEEE computer Society With advances in lithography, an
• External Research Opportunities for Georgia Tech Students Information on Transcript Listing or Course Credit
• Evaluating System-wide Monitoring Capsule Design using Xilinx Virtex-II Pro FPGA
• Profile-Guided Microarchitectural Floorplanning for Deep Submicron Processor Design
• ECE2030A Fall 2008 Prof. H.-H. S. Lee Georgia Tech Page 1 of 8
• Microprocessors continue on the relentless path to provide more performance.
• Spring 2011 President's Undergraduate Research Award (PURA) Award School Student Name Student Major Mentor Name Paper Title Funding Type
• 1 The University of Michigan Center for Parallel Computing, site of the KSR1, is partially funded by NSF grant CDA-92-14296.
• Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching
• Architecture of a 3D Software Stack for Peak Pentium III Processor Performance 1 Architecture of a 3D Software Stack for Peak Pentium III
• Execution Environment Support for Many Core Heterogeneous Accelerator Platforms
• LOCKUP-FREE INSTRUCTION FETCH/PREFETCH CACHE ORGANIZATION DAVID KROFT
• Owl: Next Generation System Monitoring Martin Schulz
• Accelerating Memory Decryption and Authentication with Frequent Value Prediction
• SAFER: Stuck-At-Fault Error Recovery for Memories Nak Hee Seong
• The Execution of Event-Action Rules on Programmable Network Processors Ada Gavrilovska, Sanjay Kumar, Karsten Schwan
• ECE 3055 Section B Computer Architecture and Operating Systems
• Forum on Education Abroad Undergraduate Research Awards
• Microarchitectural Floorplanning Under Performance and Thermal Tradeoff
• ECE2030A Fall 2008 Prof. H.-H. S. Lee Georgia Tech Page 1 of 10
• Wire-driven Microarchitectural Design Space Exploration Mongkol Ekpanyapong, Sung Kyu Lim, Chinnakrishnan Ballapuram, and Hsien-Hsin S. Lee
• Network Processors as Building Blocks in Overlay Networks Ada Gavrilovska, Karsten Schwan, Ola Nordstrom, Hailemelekot Seifu
• ADAPTIVE TRANSACTION SCHEDULING FOR TRANSACTIONAL MEMORY SYSTEMS
• President's Undergraduate Research Award (PURA) Information PLEASE READ CAREFULLY!
• February 1996 Hewlett-Packard Journal 1 Design of the HP PA 7200 CPU
• 732 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 5, MAY 2011 Low-Power Clock Tree Design for Pre-Bond
• Detection of Conflicts and Inconsistencies in Taxonomy-based Authorization Policies Apurva Mohan, Douglas M. Blough
• Proceedings of the ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems,MEMS and NEMS
• Symbiotic Scheduling for Shared Caches in Multi-Core Systems Using Memory Footprint Signature
• CACM:Current-aware Capacity Management in Consolidated Server Enclosures
• Fall 2011 President's Undergraduate Research Award (PURA) Award School Student Name
• Distributed Cloud Storage Services with FleCS Containers Hobin Yoon, Madhumitha Ravichandran, Ada Gavrilovska, Karsten Schwan
• Heterogeneous Die Stacking of SRAM Row Cache and 3-D DRAM: An Empirical Design Evaluation
• A Power Capping Controller for Multicore Processors N. Almoosa, W. Song, Y. Wardi and S. Yalamanchili
• Designing 3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores
• Designing 3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores
• BugRedux: Reproducing Field Failures for In-house Debugging Wei Jin and Alessandro Orso
• Ally: OS-Transparent Packet Inspection Using Sequestered Cores
• 1E M E R G I N G C Y B E R T H R E AT S R E P O R T 2 0 1 2 [ Table of Contents ]
• 55AUGUST 2011 PERSPECTIVES
• 188 2012 IEEE International Solid-State Circuits Conference ISSCC 2012 / SESSION 10 / HIGH-PERFORMANCE DIGITAL / 10.6
• Dae Hyun Kim1, Krit Athikulwongse1, Michael B. Healy1, Mohammad M. Hossain1, Moongon Jung1, Ilya Khorosh1, Gokul Kumar1, Young-Joon Lee1, Dean L. Lewis1,
• Global Built-In Self-Repair for 3D Memories with Redundancy Sharing and Parallel Testing
• DESIGNING HETEROGENEOUS MANY-CORE PROCESSORS TO PROVIDE HIGH PERFORMANCE
• Efficient Relational Algebra Algorithms and Data Structures for GPU (Regular Submission)
• Integrated Microarchitectural Floorplanning and Run-time Controller for Inductive Noise Mitigation