Lee, Jong Duk - School of Electrical Engineering and Computer Science, School of Electrical Engineering and Computer Science

• Process design and emission properties of gated n polycrystalline silicon field emitter arrays for flat-panel display applications
• Journal of Information Display, vol. 5, no. 4, 2004 2004 KIDS
• 150 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 1, JANUARY 2004 Synchronous Mirror Delay for Multiphase Locking
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• Reliable 2-bit=cell NVM technology using twin SONOS memory transistor
• Capacitorless DRAM Cell with Highly Scalable Surrounding Gate Structure Hoon Jeong, Yeun Seung Lee, Sangwoo Kang, Il Han Park, Woo Young Choi, Hyungcheol Shin,
• A study on the carrier injection mechanism of the bottom-contact pentacene thin film transistor
• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 4649 Effects of Electrical Stress on the Mid-Gap Interface
• INSTITUTE OF PHYSICS PUBLISHING JOURNAL OF MICROMECHANICS AND MICROENGINEERING J. Micromech. Microeng. 15 (2005) 263269 doi:10.1088/0960-1317/15/2/003
• Resistivity effect of ZnGa2O4:Mn phosphor screen on cathodoluminescence characteristics of field emission display
• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 185189 Surface-State Modification of OTFT Gate Insulators by Using
• Journal of Information Display, vol. 6, no. 2, 2005 2005 KIDS
• Reverse-Order Source/Drain Formation with Double Offset Spacer (RODOS) for CMOS Low-power, High-Speed
• Electron trap density distribution of Si-rich silicon nitride extracted using the modified negative charge decay model of silicon-oxide-nitride-
• Effective three-dimensional simulation of field emitter array and its optimal design methodology using an evolution strategy
• Sains Malaysiana 37(3)(2008): 295-298 Reliability Issues of Bottom-Contact Pentacene Thin-Film Transistors
• Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process
• 210 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003 Reverse-Order Source/Drain Formation With
• Evaluation and Resolution for Nonideal Characteristics of Complementary MetalOxideSemiconductor Devices Fabricated on Silicon-on-Insulator
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• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 8386 Body-Tied Double-Gate SONOS Flash (Omega Flash)
• Extraction of Trap Depth in Flash Cell Having Arch-Active Structure Daewoong Kang, Seungwon Yang, Byung-Gook Park, Jong Duk Lee, and Hyungcheol Shin
• 2006 29 1 Design and Simulation of Asymmetric MOSFETs
• Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire
• A Capacitor-less 1T DRAM Cell Based on a Surrounding Gate MOSFET with a Vertical Channel Hoon Jeong, Ki-Whan Song, Soo-Ho Shin*, Sang Ho Song*, Jong Duk Lee, and Byung-Gook Park
• Journal of the Korean Physical Society, Vol. 35, December 1999, pp. S693S696 Realization of Ultra-Fine Lines Using Sidewall Structures
• 247IETE TECHNICAL REVIEW | VoL 26 | ISSUE 4 | JUL-AUG 2009 Various Flash Memory Devices of Novel Design
• Scalable 2-bit siliconoxidenitrideoxidesilicon (SONOS) memory with physically separated local
• Optical characteristics of the phosphor screen in field-emission environments
• 2005 28 2 Negative-differential conductance (NDC) characteristics
• Pattern multiplication method and the uniformity of nanoscale multiple Kyung-Hoon Chung,a)
• Integration Process of Impact-Ionization MetalOxideSemiconductor Devices with Tunneling Field-Effect-Transistors and MetalOxideSemiconductor
• One can see from Table 3 that the r optimized by MGA(1) equals to that of MGA(2) for the case f 5 GHz. This result can
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 54, NO. 11, NOVEMBER 2007 2969 Design and Fabrication of Asymmetric MOSFETs
• Coulomb oscillations based on band-to-band tunneling in a degenerately doped silicon metal-oxide-semiconductor field-effect transistor
• Growth and field emission properties of carbon nanotubes on rapid thermal annealed Ni catalyst using PECVD
• IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 8, AUGUST 2007 743 Tunneling Field-Effect Transistors (TFETs) With
• Journal of the Korean Physical Society, Vol. 35, December 1999, pp. S788S790 Ultra-Thin Gate Oxide Grown on Nitrogen Implanted Silicon
• 2005 28 2 In this work, the effects of corner transistors in SOI
• Self-Aligned Dual-Gate Single-Electron Transistors Sangwoo KANG
• 70 nm SONOS Nonvolatile Memory Devices using FN Programming and Hot Hole Erase Method Soo Doo Chae1
• Metaloxidesemiconductor field effect transistor-controlled field emission display
• 8 mW 17/24 GHz dual-band CMOS low-noise amplifier for ISM-band application
• Journal of the Korean Physical Society, Vol. 49, December 2006, pp. S790S794 Negative Differential Transconductance Characteristics and
• Jpn. J. Appl. Phys. Vol. 41 (2002) pp. 44104414 Part 1, No. 6B, June 2002
• High spatial density nanocrystal formation using thin layer of amorphous Si0.7Ge0.3 deposited on SiO2
• ICSE2002 Proc. 2002, Penang, Malaysia 30 nm MOSFET Development Based on Processes
• Journal of the Korean Physical Society, Vol. 53, No. 6, December 2008, pp. 3422$3426 Dependence of Program Eciency on Channel Conditions
• IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 14, NO. 2, FEBRUARY 2004 83 Stable Extraction of Linearity (VIP 3) for
• 1380 IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 12, 2008 A Simple Figure of Merit of RF MOSFET
• Electrical aging of molybdenum field emitters Jong Duk Lee,a)
• Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 140144 Characteristics of Silicon-On-Insulator Single-Electron Transistors
• 492 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 4, JULY 2009 Fabrication and Characteristics of Self-Aligned
• IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 8, NO. 1, JANUARY 2009 111 A 2-Bit Recessed Channel Nonvolatile Memory
• Fabrication and characterization of fin SONOS flash memory with separated double-gate structure
• Full-Swing Pentacene Organic Inverter with Long-Channel Driver and Short-Channel Load
• 180 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 3, MAY 2006 Design and Optimization of Two-Bit Double-Gate
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 52, NO. 8, AUGUST 2005 1845 SET/CMOS Hybrid Process and Multiband
• Selective growth of carbon nanotubes and their application to triode-type field emitter arrays
• Effects of phosphorus implantation and subsequent growth on diamond Euo Sik Choa,*, Cheon An Leea
• IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 6, JUNE 2004 439 Silicon-Based Field-Induced Band-to-Band
• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 6064 Reverse-Order Source/Drain with Double Offset Spacer
• Journal of Information Display, vol. 4, no. 3, 2003 2003 KIDS
• Field emission properties of phosphorus doped microwave plasma chemical vapor deposition diamond films by ion implantation
• 170 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002 Single-Electron Transistors Based on Gate-Induced
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 10, OCTOBER 2002 1833 Fig. 3. Comparison of the experimental and calculated scattering parameters
• 612 IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 10, OCTOBER 2002 Negative-Differential Transconductance
• Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 8789 Synchronous Mirror Delay for Zero-and Multi-Phase Locking
• The effects of particle size and surface recombination rate on the brightness of low-voltage phosphor
• New fabrication method of silicon field emitter arrays using thermal oxidation
• 192 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 3, MAY 2006 Analytical Modeling of Field-Induced Interband
• 664 IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 11, NOVEMBER 2002 Multilevel Vertical-Channel SONOS
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• Effect of Substrate Doping Concentration on I-MOS Characteristics Woo Young Choi, Jae Young Song, Ju Hee Park,
• 178 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 2, FEBRUARY 2004 The Analysis of Dark Signals in the CMOS APS
• 258 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003 Fabrication and Program/Erase Characteristics of
• 204 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 3, MARCH 2007 Admittance Measurements on OFET Channel and
• Thin Solid Films 435 (2003) 324328 0040-6090/03/$ -see front matter 2003 Elsevier Science B.V. All rights reserved.
• 70 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 9, NO. 1, JANUARY 2010 A Vertical 4-Bit SONOS Flash Memory and a Unique
• Stable Extraction of Threshold Voltage Using Transconductance Change Method for CMOS Modeling, Simulation and Characterization
• Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized
• Extraction of Vertical, Lateral Locations and Energies of Hot-Electrons-Induced Traps through the Random Telegraph Noise
• 226 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002 A Practical SPICE Model Based on the Physics
• Programmable Virtual Source/Drain MOSFETs Byung Yong Choi*
• P-112 / K. D. Jung 1284 IMID '05 DIGEST
• Improving the Cell Characteristics and Reduction of RTS Noise Using Field Concentration Effect of Arch-Active Profile in 4 Gbits NAND Flash Array Having 60 nm Design Rule
• 69. %'%1% CFP-548 2. %SZ 'JMN 3FTJTU 3' .&.4 a CFP-039
• Extraction of Interface-States Energy Distribution in Nitrided and Pure Gate Dielectrics for Metal Oxide Semiconductor Field Effect Transistor Applications
• Journal of the Korean Physical Society, Vol. 42, No. 2, February 2003, pp. 233236 Nano-Scale SONOS Memory with a Double-Gate MOSFET Structure
• Self-Aligned Asymmetric MetalOxideSemiconductor Field Effect Transistors Fabricated on Silicon-on-Insulator
• 2006 29 1 Recently, the demand for high density MOSFET arrays are
• IEICE TRANS. ELECTRON., VOL.E91C, NO.5 MAY 2008 PAPER Special Section on Fundamentals and Applications of Advanced Semiconductor Devices
• 1282 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 5, MAY 2006 Fig. 4. Reduction of flatband voltage shift by electron injection from the gate.
• 25-nm programmable virtual source/drain MOSFETs using a twin SONOS memory structure
• An Analytic CurrentVoltage Equation for Top-Contact Organic Thin Film Transistors Including the Effects of Variable Series Resistance
• Room Temperature Carrier Transport Characteristics in Twin Silicon Nanowire MOSFETs
• Capacitorless Dynamic Random Access Memory Cell with Highly Scalable Surrounding Gate Structure
• 2006 29 1 New Capacitorless 1T DRAM Cells : Surrounding Gate and Double Gate MOSFET With
• Monte-Carlo Simulation of Single-Electron Nanocrystal Memories Jae Sung Sim, Jihye Kong , Jong Duk Lee, and Byung-Gook Park
• Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 6871 Fabrication of a 0.2-m Ultra-Thin SOI Inverted Sidewall
• Fluctuation-Robust Extended Word-line and Extended Bit-line (EWEB) NAND Flash Memory
• 246 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 2, NO. 4, DECEMBER 2003 Twin-Bit SiliconOxideNitrideOxideSilicon
• Characterization of Sensitivity and Resolution of Silicon Resistive Probe Junsoo KIM, Jaehong LEE, Ickhyun SONG, Jong Duk LEE, Byung-Gook PARK,
• Charge Trapping Characteristics of SONOS Capacitors with Control Gates of Different Work Functions during Program/Erase Operations
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• These are ``how to do it'' papers. They should be written and illustrated so that the reader may easily follow whatever instruction or advice is being given.
• Effects of Peripheral Region on C-V Characteristics of Organic MIS Capacitors
• Dark Current Characterization of the CMOS APS Imagers with Test Patterns Fabricated Using a 0.18 CMOS Technology
• 186 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 3, MAY 2006 Design Optimization of Gate-All-Around (GAA)
• Design and Optimization of Two-bit Double Gate Nonvolatile Memory Cell for Highly Reliable Operations
• Extraction of Vertical, Lateral locations and Energies of Hot-Electrons-Induced Traps Through the Random Telegraph Noise
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 3, MARCH 2009 431 Modeling and Parameter Extraction for the Series
• Fabrication of metal field emitter arrays on polycrystalline silicon II Hwan Kim and Chun Gyoo Lee
• Low turn-on voltage Mo-polycide field emitter arrays applied to field emission flat panel display
• Fabrication and characteristics of P-channel silicon-oxide-nitride-oxide-silicon flash memory device based on bulk fin shaped field effect
• JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.9, NO.1, MARCH, 2009 55 Manuscript received Feb. 28, 2009; revised Mar. 11, 2009.
• Extended Word-Line NAND Flash Memory Jang-Gn Yun
• with transmission zeros near the passband are obtained. This dual band BPF shows the advantages including size and loss reduction
• Novel Tunneling Devices with Multi-Functionality Woo Young CHOI1;2
• 1346 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 8, AUGUST 2004 resonance at fSR (i.e., the self-resonance frequency) at a high oper-
• Charge decay characteristics of silicon-oxide-nitride-oxide-silicon structure at elevated temperatures and extraction of the nitride
• IEEE ELECTRON DEVICE LETTERS, VOL. 25, NO. 5, MAY 2004 317 Twin SONOS Memory With 30-nm Storage Nodes
• Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002, pp. 908911 Multi-Level Vertical-Channel SONOS Nonvolatile Memory
• Analysis of field emission characteristics of hydrogen-adsorbed silicon surface
• Numerical analysis on field emission for the effects of the gate insulators Ho Young Ahn, Chun Gyoo Lee, and Jong Duk Lee
• De-embedding Accuracy for Interconnection Variation Jaeho Lee, Jaehong Lee, Byung Gook Park, Jong Duk Lee, and Hyungcheol Shin
• 2006 29 1 Reduction of Breakdown Voltage in I-MOS Devices
• Multi-Level Vertical Channel SONOS Nonvolatile Memory on SOI Yong Kyu Lee, Suk Kang Sung, Jae Seong Sim, Chang Ju Lee, Tae Hun Kim, Sang Hun Lee,
• 322 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 4, NO. 3, MAY 2005 A Novel Biasing Scheme for I-MOS
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004 1833 Stable Threshold Voltage Extraction Using
• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 181184 Pentacene OTFTs with PVA Gate Insulators
• Field emission properties of the polycrystalline diamond film prepared by microwave-assisted plasma chemical vapor deposition
• Semiconductor for the Green Multi-Bit Gated-Diode Flash Memory
• Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 128131 Nanoscale-Wire Patterning Using Side-Wall and
• NSM 2005 Proc. 2005, Kuching, Malaysia Challenges in Nanoscale Devices and Breakthrough
• IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 5, NO. 3, MAY 2006 201 Depletion-Enhanced Body-Isolation (DEBI)
• Superlattices and Microstructures 34 (2003) 231239 www.elsevier.com/locate/superlattices
• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 6972 Characteristics of Conventional STI Process-Related
• 1332 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 12, DECEMBER 2009 Cone-Type SONOS Flash Memory
• Low hysteresis pentacene thin-film transistors using SiO2/cross-linked poly,,vinyl alcohol... gate dielectric
• Full-swing pentacene organic inverter with long-channel driver and short-channel load Cheon An Lee, Dong-Wook Park, Keum-Dong Jung, Jong Duk Lee, and Byung-Gook Park
• Analytic equations are derived from physical quantities in the gate-source overlap region and the
• A New Stable Extraction of Threshold Voltage Using Regularization Method Woo Young Choi, Byung Yong Choi, Dong-Soo Woo, Myeong Won Lee, Jong Duk Lee, and Byung-Gook Park
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 8, AUGUST 2009 1721 Independent Double-Gate Fin SONOS Flash Memory
• P-114 / C. B. Park IMID '05 DIGEST 1291
• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 121124 A SPICE Model of Realistic Single-Electron Transistors
• Abstract The 16th Korean Conference on Semiconductors 09:00-09:20
• New approach to manufacturing field emitter arrays with sub-half-micron gate apertures
• IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 10, OCTOBER 2008 2779 Accurate Extraction of Effective Channel Length
• Fabrication and characterization of volcano-shaped field emitters surrounded by planar gates
• ICSE2006 Proc. 2006, Kuala Lumpur, Malaysia Performance Improvement of OTFTs using
• Design of Depletion Induced Body Screening (DIBS) Structure on SOI for Reliable Nanoscale NAND Flash Array
• A Simple Threshold Voltage Model for Saddle-Fin Transistor Heesang Kim
• Fabrication and analysis of a silicon tip avalanche cathode Sung Ho Jo and Jong Duk Lee
• INSTITUTE OF PHYSICS PUBLISHING NANOTECHNOLOGY Nanotechnology 15 (2004) S603S611 PII: S0957-4484(04)78360-9
• Low Hysteresis Organic Thin-Film Transistors and Inverters with Hybrid Gate Dielectric
• IEEE ELECTRON DEVICE LETTERS, VOL. 26, NO. 4, APRIL 2005 261 100-nm n-/p-Channel I-MOS Using a Novel
• Journal of the Korean Physical Society, Vol. 44, No. 1, January 2004, pp. 153156 Effects of Phosphorus Implantation and Subsequent Growth on
• 2326 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 12, DECEMBER 2000 Threshold Voltage Reduction Model
• Journal of the Korean Physical Society, Vol. 43, No. 5, November 2003, pp. 929934 Effect of Plasma Pretreatment on the Structure and Emission
• Channel width dependence of hot electron injection program/hot hole erase cycling behavior in
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• Dynamic bias temperature instability-like behaviors under FowlerNordheim program/erase stress in nanoscale silicon-oxide-nitride-oxide-silicon
• Synthetic Metals 156 (2006) 196201 Grain size effects on contact resistance of top-contact pentacene TFTs
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• IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 4, NO. 3, MAY 2005 317 Field-Induced Interband Tunneling
• Semiconductor for the Green Oscillation Period Reduction Scheme in SET Circuit Applications
• Journal of the Korean Physical Society, Vol. 41, No. 1, October 2002, pp. 497500 Fabrication of a 30-nm Planar nMOSFETs
• Highly Manufacturable and Reliable 80-nm Gate Twin SiliconOxideNitrideOxideSilicon Memory Transistor
• Abstract----Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is
• Hysteresis mechanism and reduction method in the bottom-contact pentacene thin-film transistors with cross-linked poly,,vinyl alcohol...
• Student paper 25nm Programmable Virtual Source/Drain MOSFETs Using a Twin SONOS Memory
• Electrically Stable Organic Thin-Film Transistors and Circuits Using Organic/Inorganic Double-Layer Insulator
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• Analytical Modeling of Realistic Single-Electron Transistors Based on Metal-Oxide-Semiconductor Structure with a Unique Distribution Function
• Monte Carlo Simulation of Single-Electron Nanocrystal Memories Jae Sung SIM
• Journal of the Korean Physical Society, Vol. 45, No. 5, November 2004, pp. 13001303 The Influence of Deuterium Annealing on the Evolution of
• Journal of the Korean Physical Society, Vol. 45, No. 5, November 2004, pp. 00 MOSFETs with Biased Spacer Having Different Work Function
• Novel Gate-All-Around MetalOxideSemiconductor Field Effect Transistors with Self-Aligned Structure
• On the Characteristics and Spatial Dependence of Channel Thermal Noise in Nanoscale MetalOixdeSemiconductor Field Effect Transistors
• Full-swing pentacene organic inverter with enhancement-mode driver and depletion-mode load
• IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 1, NO. 4, DECEMBER 2002 233 Electrical Characteristics of FinFET With Vertically
• Surface application of molybdenum silicide onto gated poly-Si emitters for enhanced field emission performance
• 352 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 6, NO. 3, MAY 2007 A New Capacitorless 1T DRAM Cell: Surrounding