- Generating Hardware From OpenMP Programs Y.Y. Leow, C.Y. Ng, and W.F. Wong
- Tuning SoC Platforms for Multimedia Processing: Identifying Limits and Tradeoffs
- DEP: Detailed Execution Profile , Joon Edward Sim2
- A STACK ADDRESSING SCHEME BASED ON WINDOWING Department of Information Systems
- ORION: An Adaptive Home-based Software DSM School of Computing
- Automated architecture-aware mapping of streaming applications onto GPUs
- TuneTransform Programming model
- Dynamic Cache Contention Detection in Multi-threaded Applications
- Co-synthesis of FPGA-Based Application-Specific Floating Point SIMD Accelerators
- Co-synthesis ofCo synthesis of FPGA-Based Application-Specific
- A UML 2-based Hardware-Software Co-Design Framework for Body Sensor Network Applications
- BSN Simulator: Optimizing Application Using System Level Simulation
- PiPA: Pipelined Profiling and Analysis on Multi-core Systems
- How to do a million watchpoints: Efficient Debugging using Dynamic
- VOSCH: Voltage Scaled Cache Hierarchies Weng-Fai Wong
- DRIM : A Low Power Dynamically Reconfigurable Instruction Memory Hierarchy for Embedded Systems
- Targeted Data Prefetching Weng-Fai Wong
- Dynamic Memory Optimization using Pool Allocation and Prefetching , Rodric Rabbah2
- A Performance and Power Co-optimization Approach for Modern Processors Yongxin ZHU
- Using UML 2.0 for System Level Design of Real Time SoC Platforms for Stream Processing
- Design of Clocked Circuits Using UML Abstract Clocking is an essential component of any
- Windows CE for a Reconfigurable System-on-a-Chip Processor M. R. George, and W. F. Wong
- Static Identification of Delinquent Loads Vlad-Mihai Panait
- Shell over a Cluster (SHOC): Towards Achieving Single System Image via the Shell
- A Framework for Data Prefetching using Off-line Training of Markovian Jinwoo Kim, Krishna V. Palem
- Sensitivity Analysis of a Superscalar Processor Model Y. Zhu W. F. Wong
- ORION: An Adaptive Home-based Software Distributed Shared Memory System
- Performance Analysis of Superscalar Processors Using A Queueing Model
- Optimal Placement-aware Trace-based Scheduling of Hardware Reconfigurations for FPGA Accelerators
- Co-optimization of Performance and Power in a Superscalar Processor Design
- A UML-Based Approach for Heterogeneous IP Integration Abstract -With increasing availability of predefined IP
- The Salvage Cache: A fault-tolerant cache architecture for next-generation memory technologies
- An Integrated Performance and Power Model For Superscalar Processor Designs
- Source Level Static Branch Prediction Department of Computer Science
- Cooperative instruction scheduling with linear scan register allocation
- tmPVM -Task Migratable PVM C. P. Tan, W. F. Wong, and C. K. Yuen
- The Performance Model of SilkRoad -A Multithreaded DSM System for Clusters
- Synthesizable SystemC Code from UML Models , P.S. Thiagarajan
- JAVM: Internet-based Parallel Computing Using L. F. Lau, A. L. Ananda, G. Tan, W. F. Wong
- Compiler Optimizations for Adaptive EPIC Krishna V. Palem1
- A Reconfigurable Instruction Memory Hierarchy for Embedded Systems , Hock Beng Lim2
- GUCHA: An Internet-based Parallel Computing System L. F. Lau, A. L. Ananda, G. Tan, W. F. Wong
- SilkRoad: A Multithreaded Runtime System with Software Distributed Shared Memory for SMP Clusters
- Model-driven SoC Design Via Executable UML to SystemC Kathy Dang Nguyen Zhenxin Sun P.S. Thiagarajan
- Optimizing Floating Point Operations in Scheme Department of Computer Science,
- Adaptive Schemes for Home-based DSM Systems School of Computing
- Processor Caches Built Using Multi-Level Spin-Transfer Torque RAM Cells
- Multi Retention Level STT-RAM Cache Designs with a Dynamic Refresh Scheme
- Scalable Framework for Mapping Streaming Applications onto Multi-GPU Systems
