- IEE Proceedings Computers and Digital Techniques, 153(4), July 2006, pp. 249-260. Exploiting mixed-mode parallelism for matrix operations
- IFIP WG 11.2 International Workshop on Information Security Theory and Practices: Security and Privacy of Pervasive Systems and Smart Devices,
- A Framework for Dynamic Resource Assignment and Scheduling on Reconfigurable Mixed-Mode On-Chip Multiprocessors
- VERSATILE PROCESSOR DESIGN FOR EFFICIENCY AND HIGH PERFORMANCE Sotirios G. Ziavras
- Mapping single and multiple multilevel structures onto the hypercube
- IEICE TRANS. INF. & SYST., VOL. E87-D, No. 7 JULY 2004 PAPER Special Section/Issue on Hardware/Software Support for High Performance Scientific and Engineering Computing
- Computers and Security, 2010 (Elsevier Journal) Efficient Hardware Support for Pattern Matching
- COMPUTER SYSTEMS Sotirios G. Ziavras, Department of Electrical and Computer Engineering, New Jersey
- On-Chip Vector Coprocessor Sharing for Multicores Spiridon F. Beldianu and Sotirios G. Ziavras
- Efficient Packet Classification on FPGAs also Targeting at Manageable Memory Consumption
- International Conference on Computer Vision Theory and Applications, May 2010. FPGA-BASED NORMALIZATION FOR MODIFIED GRAM-
- Customized Kernel Execution on Reconfigurable Hardware for Embedded Applications
- Reconfiguration Framework for Multi-kernel Embedded Applications Muhammad Z. Hasan and Sotirios G. Ziavras
- INTEGRATION, the VLSI journal ] (]]]]) ]]]]]] Coprocessor design to support MPI primitives in
- Performance-Energy Tradeoffs for Matrix Multiplication on FPGA-Based Mixed-Mode Chip Multiprocessors
- Resource Management for Dynamically-Challenged Reconfigurable Systems Muhammad Z. Hasan
- Parallel solution of Newton's power flow equations on configurable chips
- A HIERARCHICALLY-CONTROLLED SIMD MACHINE FOR 2D DCT ON Xizhen Xu and Sotirios G. Ziavras
- FPGA-Based Vector Processing for Solving Sparse Sets of Equations Muhammad Z. Hasan and Sotirios G. Ziavras
- Mixed-Mode Scheduling for Parallel LU Factorization of Sparse Matrices on the Reconfigurable HERA Computer
- Robust Scalability Analysis and SPM Case Studies* Dejiang Jin and Sotirios G. Ziavras
- Modeling Distributed Data Representation and its Effect on Parallel Data Accesses*
- A SUPER-PROGRAMMING TECHNIQUE FOR LARGE SPARSE MATRIX MULTIPLICATION ON PC CLUSTERS
- Processor allocation strategies for modified S.G. Ziavras
- Robot Acting on Moving Bodies (RAMBO): Interaction with Tumbling Objects
- Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs)
- ELSEVIER Parallel Computing 22 (1996) 595-606 Data broadcasting and reduction, prefix computation,
- Preventing Unwanted Social Inferences with Classification Tree Analysis Sara Motahari, Sotirios Ziavras, Quentin Jones
- Designing for Different Levels of Social Inference Risk Sara Motahari, Sotirios Ziavras, Quentin Jones
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- IEICE TRANS. INF. & SYST., VOL.E89D, NO.2 FEBRUARY 2006 PAPER Special Issue on Parallel/Distributed Computing and Networking
- H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication* Xizhen Xu and Sotirios G. Ziavras
- Powerful and Feasible Processor Interconnections With an Evaluation of Their Communications Capabilities \Lambda
- Parallel Direct Solution of Linear Equations on FPGA-Based Machines* Xiaofang Wang and Sotirios G. Ziavras
- FPGA-BASED VECTOR PROCESSOR FOR ALGEBRAIC EQUATION SOLVERS
- Load Balancing on PC Clusters with the Super-Programming Model * Dejiang Jin and Sotirios G. Ziavras
- Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
- UNCORRECTEDPROOF Future Generation Computer Systems 795 (2000) 118
- IEEE Transactions on Information Forensics & Security, Vol. 5, No. 3, September 2010, pp. 570-580. 1 Online Anonymity Protection in Computer-Mediated
- HERA: A RECONFIGURABLE AND MIXED-MODE PARALLEL COMPUTING ENGINE ON PLATFORM FPGAS*
- FPGA IMPLEMENTATION OF A CHOLESKY ALGORITHM FOR A SHARED-MEMORY MULTIPROCESSOR ARCHITECTURE*
- Performance Optimization of an FPGA-Based Configurable Multiprocessor for Matrix Operations*
- Euromicro Conference on Digital System Design: Architectures, Methods and Tools, September 2010.
- WARFP05 ziavras@njit.edu 1 Intra-and Inter-FPGA Programmable
- HISTORY OF COMPUTATION Sotirios G. Ziavras, Department of Electrical and Computer Engineering, New Jersey
- System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
- A Configurable Multiprocessor and Dynamic Load Balancing for Parallel LU Factorization*
- Social Inference Risk Modeling in Mobile and Social Applications
- Concurrency and Computation: Practice and Experience, 16(4), April 2004, pp. 319-343. Parallel LU Factorization of Sparse Matrices
- ON THE MAPPING PROBLEM FOR MULTI-LEVEL SYSTEMS Sotirios G. Ziavras
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 7, JULY 2009 953 On the Exploitation of Narrow-Width Values for
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- This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
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