- Implicitly-Multithreaded Processors Il Park, Babak Falsafi and T. N. Vijaykumar
- Reducing Register Ports for Higher Speed and Lower Energy Il Park, Michael D. Powell, and T. N. Vijaykumar
- This research was sponsored in part by Semiconductor Research Corporation, Intel, and IBM.
- Reducing Design Complexity of the Load/Store Queue Il Park, Chong Liang Ooi, and T. N. Vijaykumar
- Reactive-Associative Caches While set-associative caches typically incur fewer
- Optimizing Replication, Communication, and Capacity Allocation in CMPs Zeshan Chishti, Michael D. Powell, and T. N. Vijaykumar
- Efficient Use of Memory Bandwidth to Improve Network Processor Throughput Jahangir Hasan Satish Chandra 1 T. N. Vijaykumar
- Multiplex: Unifying Conventional and Speculative Thread-Level Parallelism on a Chip Multiprocessor
- An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches
- Speculative Versioning Cache Sridhar Gopal y T.N.Vijaykumar \Lambda James E. Smith z Gurindar S. Sohi y
- Dynamic Pipelining: Making IP-Lookup Truly Scalable {hasanj, vijay} @ecn.purdue.edu
- Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage
- Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories
- Prevention and Detection of Stack Buffer Overflow Attacks Benjamin A. Kuperman
- A Program Transformation and Architecture Support for Quantum Uncomputation
- Ethan Schuchman and T. N. Vijaykumar School of Electrical and Computer Engineering, Purdue University
- Heat Stroke: Power-Density-Based Denial of Service in SMT Jahangir Hasan Ankit Jalote T. N. Vijaykumar Carla E. Brodley1
- Chen-Yong Cher and T. N. Vijaykumar School of Electrical and Computer Engineering, Purdue University, {chenyong,vijay}@ecn.purdue.edu
- Exploiting Reference Idempotency to Reduce Speculative Storage Overflow
- Resource Area Dilation to Reduce Power Density in Throughput Michael D. Powell1
- AN ENERGY-EFFICIENT HIGH-PERFORMANCE DEEP-SUBMICRON INSTRUCTION CACHE Se-Hyun Yang, Michael Powell, Babak Falsafi, Kaushik Roy, and T. N. Vijaykumar
- Pesticide: Using SMT to Improve Performance of Pointer-Bug Detection Jin-Yi Wang, Yen-Shiang Shue, T. N. Vijaykumar, and Saurabh Bagchi
- To appear in the 31st International Symposium on Microarchitecture, Dec. 1998 Task Selection for a Multiscalar Processor
- Opportunistic Transient-Fault Detection Mohamed A. Gomaa and T. N. Vijaykumar
- Shapeshifter: Dynamically Changing Pipeline Width and Speed to Address Process Variations*
- Automatic Volume Management for Programmable Microfluidics Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar
- BlackJack: Hard Error Detection with Redundant Threads on SMT Ethan Schuchman and T. N. Vijaykumar
- AquaCore: A Programmable Architecture for Microfluidics Ahmed M. Amin, Mithuna Thottethodi, T. N. Vijaykumar
- Speculative Thread Decomposition Through Empirical Optimization
- SmashGuard: A Hardware Solution to Prevent Security Attacks on the Function Return Address
- W. Grass et al. (Eds.): ARCS 2006, LNCS 3894, pp. 232 251, 2006. Springer-Verlag Berlin Heidelberg 2006
- Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines Michael D. Powell, Ethan Schuchman and T. N. Vijaykumar
- Min-Cut Program Decomposition for Thread-Level Speculation
- Exploiting Resonant Behavior to Reduce Inductive Noise To appear in the 31st International Symposium on Computer Architecture (ISCA 31), June 2004
- Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures
- Pipeline Muffling and A Priori Current Ramping: Architectural Techniques to Reduce High-Frequency Inductive Noise
- Efficient Use of Memory Bandwidth to Improve Network Processor Throughput Jahangir Hasan Satish Chandra
- Transient-Fault Recovery for Chip Multiprocessors Mohamed Gomaa, Chad Scarbrough, T. N. Vijaykumar, and Irith Pomeranz
- Accelerating Private-Key Cryptography via Multithreading on Symmetric Multiprocessors
- Task Selection for the Multiscalar Architecture The Multiscalar architecture advocates a distributed processor organization and task-level speculation to
- Heat-and-Run: Leveraging SMT and CMP to Manage Power Density Through the Operating System
- Adaptive Flow Control for Robust Performance and Energy Syed Ali Raza Jafri
- Joint Optimization of Idle and Cooling Power in Data Centers While Maintaining Response Time
- EffiCuts: Optimizing Packet Classification for Memory and Throughput
- Timetraveler: Exploiting Acyclic Races for Optimizing Memory Race Recording
