Roth, Amir - Department of Computer and Information Science, University of Pennsylvania

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Roth, Amir - Department of Computer and Information Science, University of Pennsylvania

Journal of Instruction Level Parallelism 3 (2001) Submitted 11/01; published 4/02 Register integration (or simply integration) is a mechanism for the direct reuse of previously computed
Appears in Proceedings of PACT-18, Sep. 2009. CPROB: Checkpoint Processing with Opportunistic Minimal Recovery
Current techniques for prefetching linked data structures (LDS) exploit the work available in one loop iteration or
Register integration (or simply integration) is a mechanism for incorporating speculative results directly into a sequential
Appears in Proceedings of MoBS-5, Jun. 2009. FIESTA: A Sample-Balanced Multi-Program Workload Methodology
Physical Register Reference Counting Department of Computer and Information Science, University of Pennsylvania
MS-CIS-04-08, Roth, A High-Bandwidth Load-Store Unit for Single-and Multi-Threaded Processors 1 A store queue (SQ) is a critical component of the load execution machinery. High ILP processors require
Amir Roth Page 1 of 2 2001 Doctorate of Philosophy in Computer Science
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential pro-
The decoupled access/execute architecture described a machine that enables the access of memory values to be
Micro-architectural techniques of the next decade will have to be more efficient and scalable in order to handle
University of Pennsylvania, Department of Computer and Information Sciences Technical Report MS-CIS-02-22 available at http://www.cis.upenn.edu/~amir/pubs/tr/rix-tr2002.pdf
Improving Virtual Function Call Target Prediction via Dependence-Based Pre-Computation
Appears in Proceedings of HPCA-15, Feb. 2009. iCFP: Tolerating All-Level Cache Misses in In-Order Processors
Encoding Mini-Graphs with Handle Prefix Outlining Anne Weinberger Bracy and Amir Roth
University of Pennsylvania, Department of Computer and Information Science Technical Report MS-CIS-02-23 available at http://www.cis.upenn.edu/~amir/pubs/tr/tselect-tr2002.pdf
Appears in proceedings of 32nd International Symposium on Computer Architecture (ISCA-32), Jun. 2005. RENO: A Rename-Based Instruction Optimizer