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Pan, David Z. - Department of Electrical and Computer Engineering, University of Texas at Austin
RADAR: RET-Aware Detailed Routing Using Fast Lithography Simulations
Diffusion-Based Placement Migration Haoxing Ren
Sleep Transistor Sizing Using Timing Criticality and Temporal Currents
Redundant-Via Enhanced Maze Routing for Yield Improvement
True Crosstalk Aware Incremental Placement with Noise Map
A Multi-objective Floorplanner for Shuttle Mask Optimization , Ruiqi Tianb
Pushing ASIC Performance in a Power Envelope Ruchir Puri, Leon Stok, John Cohn
Interconnect-Driven Floorplanning with Fast Global Wiring Planning and Optimization
Interconnect Design for Deep Submicron ICs , Zhigang Pan, Lei He, Cheng-Kok Koh and Kei-Yong Khoo
Buffer Block Planning for Interconnect Planning and Prediction Jason Cong, Tianming Kong and David Zhigang Pan
Improved Crosstalk Modeling with Applications to Noise Constrained Interconnect Optimization
Sensitivity Guided Net Weighting for Placement Driven Synthesis
Manufacturability-Aware Physical Layout Optimizations
Sensitivity Guided Net Weighting for Placement Driven Synthesis
Interconnect Delay and Area Estimation for Multiple-Pin Nets
Interconnect Estimation and Planning for Deep Submicron Designs
Buffer Block Planning for Interconnect-Driven Floorplanning Jason Cong, Tianming Kong and David Zhigang Pan
CMPAware Shuttle Mask Floorplanning Abstract -By putting different chips on the same mask, shuttle
Global Interconnect Sizing and Spacing with Consideration of Coupling Capacitance
