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Martínez, José F. - Computer Systems Laboratory & School of Electrical and Computer Engineering, Cornell University
Appears in Intl. Symp. on Computer Architecture (ISCA), pp. 13-24, June 2000. Architectural Support for Scalable Speculative Parallelization in
A Power-efficient All-optical On-chip Interconnect Using Wavelength-based Oblivious Routing
Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors
Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors
Checkpointed Early Load Retirement Nevin Kirman Meyrem Kirman Mainak Chaudhuri
Adrin Cristal , Jos F. Martnez
Appears in Intl. Conf. on Supercomputing (ICS), pp. 202-209, June 1999. Improving the Performance of Bristled CC-NUMA Systems
Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors
Scavenger: A New Last Level Cache Architecture with Global Block Priority Arkaprava Basu
Speculative Synchronization: Applying Thread-Level Speculation to Explicitly Parallel Applications
Toward Kilo-instruction Processors ADRI AN CRISTAL, OLIVERIO J. SANTANA, and MATEO VALERO
Cherry: Checkpointed Early Resource Recycling in Out-of-order Microprocessors
Parallel applications require carefully synchronized threads for execute correctly. To
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors
Self-Optimizing Memory Controllers: A Reinforcement Learning Approach Engin Ipek1,2
Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine
MORSE: Multi-objective Reconfigurable Self-optimizing Memory Scheduler
