- REGISTER ALLOCATION & SPILLING VIA GRAPH COLORING G. J. Chaitin
- Code Size Minimization and Retargetable Assembly for Custom EPIC and VLIW Instruction Formats
- PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators
- The Partial Reverse If-Conversion Framework for Balancing Control Flow and Predication
- An Automatic System for Application-Specific Instruction Format Design and Code Generation for VLIW and EPIC processors
- Region-based Hierarchical Operation Partitioning for Multicluster Processors
- [file:]function descriptions
- HARDWARE/SOFTWARE TECHNIQUES FOR MEMORY POWER OPTIMIZATIONS
- 1 Introduction 1.1 Predicated execution
- Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems
- The Program Dependence Graph and Its Use in Optimization
- HPL-PD Architecture Specification: Version 1.1
- SOFTWARE--PRACTICE AND EXPERIENCE, VOL. 28(8), 128 (July 1998) Practical Improvements to the Construction and
- Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures
- Appears in Adv. in Lang. and Comp. for Par. Proc., Banerjee, Gelernter, Nicolau, and Padua ed 1 Using Pro le Information to Assist Advanced
- Compiler Synthesized Dynamic Branch Prediction Scott Mahlke Balas Natarajan
- Bitwidth Sensitive Code Generation in a Custom Embedded Accelerator Design System Scott Mahlke Rajiv Ravindran Michael Schlansker Robert Schreiber Timothy Sherwood
- Trace Selection for Compiling Large C Application Programs to Pohua P. Chang
- COOPERATIVE DATA AND COMPUTATION PARTITIONING FOR
- Machine-Description Driven Compilers for EPIC Processors
- Elcor's Machine Description System: Version 3.0
- Self-calibrating Online Wearout Detection Jason Blome Shuguang Feng Shantanu Gupta Scott Mahlke
- Uncovering Hidden Loop Level Parallelism in Sequential Applications Hongtao Zhong, Mojtaba Mehrara, Steve Lieberman, and Scott Mahlke
- Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping Nathan Clark1
- CUSTOMIZING THE COMPUTATION CAPABILITIES OF MICROPROCESSORS
- c Copyright by Scott Alan Mahlke, 1996 EXPLOITING INSTRUCTION LEVEL PARALLELISM
- Exploring the Design Space of LUT-based Transparent Accelerators
- Achieving High Levels of Instruction-Level Parallelism with Reduced Hardware Complexity
- A Study of the E ects of Compiler-Controlled Speculation on Instruction and Data Caches
- Sentinel Scheduling: A Model for Compiler-Controlled Speculative Execution
- An E cient Architecture for Loop Based Data Preloading William Y. Chen Roger A. Bringmann Scott A. Mahlke Richard E. Hank James E. Sicolo
- Trimaran: A Compiler and Simulator for Research on Embedded and EPIC Architectures
- Control CPR: A Branch Height Reduction Optimization for EPIC Architectures
- Using Pro le Information to Assist Classic Code Optimizations Pohua P. Chang, Scott A. Mahlke, and Wen-mei W. Hwu
- Proceedings of the ACM PLDI Conference, Albuquerque, New Mexico, June, 1993, pp. 290-299. 1 Reverse If-Conversion
- EPIC: An Architecture for Instruction-Level Parallel Processors
