Kozyrakis, Christos - Departments of Electrical Engineering & Computer Science, Stanford University

• SERVER ENGINEERING INSIGHTS FOR LARGE-SCALE ONLINE SERVICES
• Phoenix++: Modular MapReduce for Shared-Memory Systems
• Appears in the Proceedings of the 43rd Annual IEEE/ACM Symposium on Microarchitecture (MICRO-43), 2010 The ZCache: Decoupling Ways and Associativity
• Building and Using the ATLAS Transactional Memory System Njuguna Njoroge, Sewook Wee, Jared Casper, Justin Burdick, Yuriy Teslyar,
• An Effective Hybrid Transactional Memory System with Strong Isolation Guarantees
• A Comparison of High-Level Full-System Power Models Suzanne Rivoire
• A Practical FPGA-based Framework for Novel CMP Sewook Wee, Jared Casper, Njuguna Njoroge, Yuriy Tesylar, Daxia Ge
• Two trends call into question the cur-rent practice of fabricating micro-
• With uniprocessor systems running into instruction-level parallelism (ILP) limits
• High-Performance Architectures for Embedded Memory Systems
• Storage I/O Generation and Replay for Datacenter Applications
• Understanding Sources of Inefficiency in General-Purpose Chips
• FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures
• Appears in the Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS 2010) Evaluating Bufferless Flow Control for On-Chip Networks
• An Analysis of On-Chip Interconnection Networks for Large-Scale
• Implementing and Evaluating a Model Checker for Transactional Memory Systems
• Future Scaling of Processor-Memory Interfaces Jung Ho Ahn
• On the Energy (In)efficiency of Hadoop Clusters Jacob Leverich, Christos Kozyrakis
• Decoupling Dynamic Information Flow Tracking with a Dedicated Coprocessor Hari Kannan Michael Dalton Christos Kozyrakis
• Fast Memory Snapshot for Concurrent Programming without Synchronization
• Real-World Buffer Overflow Protection for Userspace & Kernelspace Michael Dalton, Hari Kannan, Christos Kozyrakis
• Improving Software Concurrency with Hardware-assisted Memory Snapshot
• A Low Power Front-End for Embedded Processors Using a Block-Aware Instruction Set
• RakshaRaksha
• Raksha: A Flexible Information Flow Architecture for Software Security
• Comparing Memory Systems for Chip Multiprocessors Jacob Leverich Hideho Arakida Alex Solomatnikov
• ATLAS: A Chip-Multiprocessor with Transactional Memory Support Njuguna Njoroge, Jared Casper, Sewook Wee, Yuriy Teslyar,
• Science of Computer Programming 63 (2006) 111129 www.elsevier.com/locate/scico
• Testing Implementations of Transactional Memory Chaiyasit Manovit
• Early Release: Friend or Foe? Travis Skare and Christos Kozyrakis
• Heuristics for Profile-driven Method-level Speculative Parallelization John Whaley and Christos Kozyrakis
• Stream Virtual Machine and Two-Level Compilation Model for Streaming Architectures and Languages
• The Stream Virtual Machine Francois Labonte
• Overcoming the Limitations of Conventional Vector Processors Christos Kozyrakis
• In the Proceedings of the 35th International Symposium on Microarchitecture, Instabul, Turkey, November 2002 Vector Vs. Superscalar and VLIW Architectures
• Scalable Vector Media-processors for Embedded Systems
• Exploiting On-Chip Memory Bandwidth in the VIRAM Compiler
• A Media-Enhanced Vector Architecture for Embedded Memory Systems
• 0018-9162/98/$10.00 1998 IEEE24 Computer A New Direction for
• THE DESIGN AND IMPLEMENTATION OF DYNAMIC INFORMATION FLOW TRACKING SYSTEMS
• ATLAS: SOFTWARE DEVELOPMENT ENVIRONMENT FOR HARDWARE TRANSACTIONAL MEMORY
• BLOCK-AWARE INSTRUCTION SET ARCHITECTURE
• ARCHITECTURES FOR TRANSACTIONAL MEMORY A DISSERTATION
• Register Pointer Architecture for Efficient Embedded Processors JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer
• Energy-Efficient and High-Performance Instruction Fetch using a Block-Aware ISA
• Tainting is Not Pointless Michael Dalton, Hari Kannan, Christos Kozyrakis
• Comparative Evaluation of Memory Models for Chip Multiprocessors
• Scalable Vector Media-processors for Embedded Systems
• The Energy Efficiency of IRAM Architectures Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis,
• Accurate Modeling and Generation of Storage I/O for Datacenter Workloads Christina Delimitrou1
• The Case for RAMClouds: Scalable High-Performance Storage Entirely in DRAM
• Transactional Coherence and Consistency (TCC) offers a way to simplify parallel programming by executing all code within trans-
• Transactional Execution of Java Programs Brian D. Carlstrom, JaeWoong Chung, Hassan Chafi, Austen McDonald, Chi Cao Minh
• Improving Instruction Delivery with a Block-Aware ISA Ahmad Zmily, Earl Killian, and Christos Kozyrakis
• DESIGNING AN EFFECTIVE HYBRID TRANSACTIONAL MEMORY SYSTEM
• EigenBench: A Simple Exploration Tool for Orthogonal TM Characteristics
• The Software Stack for Transactional Memory Challenges and Opportunities
• 0018-9162/07/$25.00 2007 IEEE December 2007 39Published by the IEEE Computer Society circuit techniques such as disabling the clock signal
• From Chaos to QoS: Case Studies in CMP Resource Management Hari Kannan!
• Hardware/Compiler Codevelopment for an Embedded Media Processor
• Tradeoffs in Transactional Memory Virtualization JaeWoong Chung, Chi Cao Minh, Austen McDonald, Travis Skare,
• Hot topic session: How to solve the current memory access and data transfer bottlenecks: at the
• Library-based Prefetching for Pointer-intensive Applications Varun Malhotra and Christos Kozyrakis
• Brief Announcement: Towards Soft Optimization Techniques for Parallel Cognitive Applications
• Power Management of Datacenter Workloads Using Per-Core Power Gating
• Implementing and Evaluating Nested Parallel Transactions in Software Transactional Memory
• Thread-Safe Dynamic Binary Translation using Transactional Memory JaeWoong Chung, Michael Dalton, Hari Kannan, Christos Kozyrakis
• Characterization of TCC on Chip-Multiprocessors Austen McDonald, JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Brian D. Carlstrom
• Simultaneously Improving Code Size, Performance, and Energy in Embedded Processors
• Full-System Power Analysis and Modeling for Server Environments
• Vantage: Scalable and Efficient Fine-Grain Cache Partitioning Daniel Sanchez and Christos Kozyrakis
• The ATOMO Transactional Programming Language Brian D. Carlstrom Austen McDonald Hassan Chafi
• The OpenTM Transactional Application Programming Interface Woongki Baek, Chi Cao Minh, Martin Trautmann,
• The Common Case Transactional Behavior of Multithreaded Programs JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom
• Block-Aware Instruction Set Architecture AHMAD ZMILY and CHRISTOS KOZYRAKIS
• IMPROVING THE PRACTICALITY OF TRANSACTIONAL MEMORY
• Parallelizing SPECjbb2000 with Transactional Memory JaeWoong Chung, Chi Cao Minh, Brian D. Carlstrom, Christos Kozyrakis
• Transactional Programming In A Multi-core Environment
• THE DESIGN AND IMPLEMENTATION OF HARDWARE SYSTEMS FOR INFORMATION FLOW TRACKING
• TAPE: A Transactional Application Profiling Environment Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D. Carlstrom, JaeWoong Chung, Lance Hammond,
• Hardware Enforcement of Application Security Policies Using Tagged Memory
• Designers of embedded processors have typically optimized for low power con-
• ASeD: Availability, Security, and Debugging Support using Transactional Memory
• Nemesis: Preventing Authentication & Access Control Vulnerabilities in Web Applications
• Hardware Acceleration of Transactional Memory on Commodity Systems
• Deconstructing Hardware Architectures for Security Michael Dalton Hari Kannan Christos Kozyrakis
• SYSTEM CHALLENGES AND OPPORTUNITIES FOR TRANSACTIONAL MEMORY
• A Scalable, Non-blocking Approach to Transactional Memory Hassan Chafi Jared Casper Brian D. Carlstrom
• Making Nested Parallel Transactions Practical using Lightweight Hardware Support
• VIRAM1: A Media-Oriented Vector Processor with Embedded DRAM
• Autonomic Power Management Schemes for Internet Servers and Data Centers
• In this paper, we propose a new shared memory model: Transac-tional memory Coherence and Consistency (TCC). TCC pro-
• JouleSort: A Balanced Energy-Efficiency Benchmark Suzanne Rivoire
• Vector Lane Threading Suzanne Rivoire, Rebecca Schultz, Tomofumi Okuda
• ASeD: Availability, Security, and Debugging Support using Transactional Memory
• Modeling and Replay of Storage I/O for Datacenter Workloads
• MODELS AND METRICS FOR ENERGY-EFFICIENT COMPUTER SYSTEMS
• High-Performance Architectures for Embedded Memory Systems
• Phoenix Rebirth: Scalable MapReduce on a Large-Scale Shared-Memory System
• Feedback-Directed Barrier Optimization in a Strongly Isolated STM
• Energy Dumpster Diving Maria A. Kazandjieva, Brandon Heller, Philip Levis, Christos Kozyrakis
• A Memory System Design Framework: Creating Smart Memories
• Flexible Architectural Support for Fine-Grain Scheduling Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis
• Evaluating MapReduce for Multi-core and Multiprocessor Systems Colby Ranger, Ramanan Raghuraman, Arun Penmetsa, Gary Bradski, Christos Kozyrakis
• Computer Science Division University of California at Berkeley
• STAMP: Stanford Transactional Applications for Multi-Processing
• oCTobEr 2011 | voL. 54 | No. 10 | communications of the acm 85 Doi:10.1145/2001269.2001291
• Decoupling Datacenter Studies from Access to Large-Scale Applications: A Modeling Approach for Storage Workloads
• SCD: A Scalable Coherence Directory with Flexible Sharer Set Encoding Daniel Sanchez and Christos Kozyrakis