- Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors
- A Performance-Correctness Explicitly-Decoupled Architecture Alok Garg and Michael C. Huang
- Supporting Highly-Decoupled Thread-Level Redundancy for Parallel Programs M. Wasiur Rashid and Michael C. Huang
- Software-Hardware Cooperative Memory Disambiguation Ruke Huang, Alok Garg, and Michael Huang
- Positional Adaptation of Processors: Application to Energy Reduction Michael C. Huang
- Variation-Tolerant Hierarchical Voltage Monitoring Circuit for Soft Error Detection
- A Memory Soft Error Measurement on Production Systems Xin Li Kai Shen Michael C. Huang
- An Empirical Study of Memory Hardware Errors in A Server Farm Xin Li Michael C. Huang Kai Shen
- Memory Buffer Element Optimization for Decoupled Thread Level Redundancy
- Practicality of Single Event Effects Detection using thin-films: A Study
- Interaction between Communication-based and Capacity-based Coherence Protocol Optimizations
- Exploiting Timing Properties of Memory Access for Efficient Dependence Enforcement
- Slackened Memory Dependence Enforcement: Combining Opportunistic Forwarding with Decoupled Verification
- Implementation Issues of Slackened Memory Dependence Enforcement Technical Report
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 9, SEPTEMBER 2008 1251 [3] A. Castro, M. Nicolaidis, P. Lestrat, and B. Courtois, "Built-in self test
- Dynamically Reducing Pressure on the Physical Register File through Simple Register Sharing
- Variation Tolerant Hierarchical Voltage Monitoring Circuit for Soft Error Detection
- DMDC: Delayed Memory Dependence Checking through Age-Based Filtering Fernando Castro, Luis Pinuel, Daniel Chaver, Manuel Prieto, Michael Huang, Francisco Tirado
- Highly-Decoupled Thread Level Redundancy Muhammad Wasiur Rashid
- Substituting Associative Load Queue with Simple Hash Tables in Out-of-Order Microprocessors
- Binary Analysis and Optimization for Explicitly Decoupled Architectures
