- Compiler Blockability of Numerical Algorithms* Ken Kennedy
- CRAIG: A Practical Framework for Combining Instruction Scheduling and Register Thomas S. Brasier Philip H. Sweany Steven J. Beaty
- Loop Transformations for Architectures with Partitioned Register Banks
- A Code Generation Framework for VLIW Architectures with Partitioned Register Banks \Lambda
- Compiler Optimizations for Improving Data Locality Kathryn S. McKinleySteve Cam Chau-Wen Tseng
- Caching and Predicting Branch Sequences for Improved Fetch E ectiveness
- Fast Branch Misprediction Recovery in Out-of-order Superscalar Processors
- Feedback-directed Memory Disambiguation Through Store Distance Analysis
- Compiling Scientific Code for Complex Memory Hierarchies \Lambda Ken Kennedy
- Superscalar Execution With Dynamic Data Forwarding \Lambda Onder Rajiv Gupta
- Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing
- Automatic Generation of Microarchitecture Simulators \Lambda Onder Rajiv Gupta
- Evaluating Register Bank Partitioning with Genetic Algorithms Dineel Sule Steve Carr y Philip Sweany z
- The Design and Construction of a UserLevel Kernel for Teaching Multithreaded Programming
- Load and Store Reuse Using Register File Contents
- Modulo Scheduling with Cache Reuse Information ?
- Combining Optimization for Cache and InstructionLevel Parallelism \Lambda Department of Computer Science
- Optimizing Loop Performance for Clustered VLIW Architectures Department of Computer Science
- Value Cloning For Architectures with Partitioned Register Banks \Lambda (Extended Abstract)
- ConcurrentMentor: A Visualization System for Distributed Programming Education
- Improving Software Pipelining with Hardware Support for SelfSpatial Loads Philip Sweany
- BLOCKING LINEAR ALGEBRA CODES FOR MEMORY HIERARCHIES \Lambda
- ThreadMentor: A Pedagogical Tool for Multithreaded Programming
- Global Register Partitioning Jason Hiser
- Race Conditions: A Case Study Steve Carr, Jean Mayo and Ching-Kuang Shene
- IMPROVING SOFTWARE PIPELINING BY HIDING MEMORY LATENCY WITH
- Instruction Wake-Up in Wide Issue Superscalars Onder 1 and Rajiv Gupta 2
- Dynamic Memory Disambiguation in the Presence of Out-of-order Store Issuing
- RETROSPECTIVE: Improving Register Allocation for Subscripted Variables
- Compiler Blockability of Dense Matrix Factorizations
- Improving the Ratio of Memory operations to Floating-Point Operations in Loops
- Register Pressure Guided Unroll-and-Jam Yin Ma Steve Carr
- Instruction Based Memory DistanceAnalysis and its Application to Optimization* Changpeng Fang Steve Soner Onder Zhenlin Wang
- Reuse-distance-based Miss-rate Prediction on a Per Instruction Basis
- Loop Fusion for Clustered VLIW Architectures Department of Computer
- Channels, Visualization, and Topology Editor Steve Carr, Ping Chen, Timothy R. Jozwowski, Jean Mayo and Ching-Kuang Shene
- A Communication Library to Support Concurrent Programming Steve Carr, Changpeng Fang, Tim Jozwowski, Jean Mayo and Ching-Kuang Shene
- A Portable Class Library for Teaching Multithreaded Programming*
- A Visualization System for Multithreaded Programming* Michael Bedy, Steve Carr, Xianglong Huang and Ching.Kuang Shenet
- Improving Register Allocation for Subscripted Variables* David Callahan+ Steve CarrS Ken Kennedy4
- Path-Based Reuse Distance Analysis Changpeng Fang1, Steve Carr2, Soner Onder2, and Zhenlin Wang2
- Low-cost Register-pressure Prediction for Scalar Replacement Using Pseudo-schedules
- Improving Data Locality with Loop Transformations KATHRYN S. McKINLEY
- Scalar Replacement in the Presence of Conditional Control Flow STEVE CARR y and KEN KENNEDY
- Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
- A Case for a Working-set-based Memory Hierarchy Department of Computer Science
- Register Assignment for Software Pipelining with Partitioned Register Banks Jason Hiser
- I-. -`.-----_--Unroll-and-Jam Using Uniformly GeneratedSets
- A Compiler-Blockable Algorithm for QR Decomposition Steve Carr y R. B. Lehoucq z
- THE DESIGN OF A MULTITHREADED PROGRAMMING COURSE AND ITS ACCOMPANYING SOFTWARE TOOLS
- Automatic Generation of Microarchitecture Simulators \Lambda Onder Rajiv Gupta
- Optimizing Static Power Dissipation by Functional Units in Superscalar Processors ?
- Improving Software Pipelining With UnrollandJam \Lambda Philip Sweany
- Automatic Data Partitioning for the Agere Payload Plus Network Processor
- TEACHING ACCESS CONTROL WITH DOMAIN TYPE ENFORCEMENT Steve Carr, Jean Mayo
