- Efficient Architectures through Application Clustering and Architectural Heterogeneity
- Copyright 2008 American Scientific Publishers All rights reserved
- Integrated Analysis of Power and Performance for Pipelined Microprocessors
- Architectural Power Models for SRAM and CAM Structures Based on Hybrid Analytical/Empirical Techniques
- Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance
- Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network
- An Adaptive Issue Queue for Reduced Power at High Performance Alper Buyuktosunoglu *, 2 , Stanley Schuster 1 , David Brooks 1 , Pradip Bose 1 , Peter Cook 1 , and David Albonesi 2
- Tribeca: Design for PVT Variations with Local Recovery and Fine-grained Adaptation
- POWER, THERMAL, AND RELIABILITY MODELING IN NANOMETER-SCALE
- Efficiency Trends and Limits from Comprehensive Microarchitectural Adaptivity
- Power and Thermal Effects of SRAM vs. Latch-Mux Design Styles and Clock Gating Choices
- A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
- Eliminating Voltage Emergencies via Microarchitectural Voltage Control Feedback and Dynamic Optimization
- Process Variation Tolerant Register Files Based On Dynamic Memories
- TinyBench: The Case For A Standardized Benchmark Suite for TinyOS Based Wireless Sensor Network Devices
- Process Variation Tolerant 3T1D-Based Cache Architectures Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei and David Brooks
- An Accelerator-Based Wireless Sensor Network Processor in 130nm CMOS
- Evaluating Techniques for Exploiting Instruction Slack Yau Chin, John Sheu, and David Brooks
- Eliminating Voltage Emergencies via Software-Guided Code Transformations
- PREDICTING VOLTAGE DROOPS USING RECURRING PROGRAM
- Applied Inference: Case Studies in Microarchitectural Design
- Design and Test Strategies for Microarchitectural Post-Fabrication Tuning
- Software-Assisted Hardware Reliability: Abstracting Circuit-level Challenges to the Software Stack
- Thread Motion: Fine-Grained Power Management for Multi-Core Systems
- An Event-Guided Approach to Reducing Voltage Noise in Processors
- Voltage Noise: Why It's Bad, and What To Do About It Vijay Janapa Reddi, Meeta S. Gupta, Krishna K. Rangan, Simone Campanoni, Glenn Holloway,
- Energy-and Area-Efficient Architectures through Application Clustering and
- Evaluation of Voltage Interpolation to Address Process Variations
- Instruction-Driven Clock Scheduling with Glitch Mitigation Gu-Yeon Wei, David Brooks, Ali Durlov Khan and Xiaoyao Liang
- ReVIVaL: A Variation-Tolerant Architecture Using Voltage Interpolation and Variable Latency
- DeCoR: A Delayed Commit and Rollback Mechanism for Handling Inductive Noise in Processors
- 404 2008 IEEE International Solid-State Circuits Conference 22.3 A Process-Variation-Tolerant Floating-Point Unit
- Towards a Software Approach to Mitigate Voltage Emergencies
- Illustrative Design Space Studies with Microarchitectural Regression Models Benjamin C. Lee and David M. Brooks
- Architecture and Circuit Techniques for Low-Throughput, Energy-Constrained Systems Across Technology
- Effects of Pipeline Complexity on SMT/CMP Power-Performance Efficiency Benjamin Lee and David Brooks
- Understanding the Energy Efficiency of Simultaneous Multithreading
- V. Srinivasan M. K. Gschwind
- We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being
- A Circuit Level Implementation of an Adaptive Issue for Power-Aware Microprocessors
- An Ultra Low Power System Architecture for Sensor Network Applications Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu-Yeon Wei, David Brooks
- Mitigating the Impact of Process Variations on Processor Register Files and Execution Units
- Power-Performance Simulation: Design and Validation David Brooks
- Empirical Performance Models for 3T1D Memories Kristen Lovin
- CPR: Composable Performance Regression for Scalable Multiprocessor Models Benjamin C. Lee
- Roughness of Microarchitectural Design Topologies and its Implications for Optimization
- Methods of Inference and Learning for Performance Modeling of Parallel Applications
- CMP Design Space Exploration Subject to Physical Constraints , Benjamin Lee
- System Level Analysis of Fast, Per-Core DVFS using On-Chip Switching Regulators
- Control Techniques to Eliminate Voltage Emergencies in High Performance Processors
- Dynamic Thermal Management for High-Performance Microprocessors David Brooks
- Place and Route Considerations for Voltage Interpolated Designs Kevin Brownell, Ali Durlov Khan, David Brooks, Gu-Yeon Wei
- Statistically Rigorous Regression Modeling for the Microprocessor Design Space Benjamin C. Lee, David M. Brooks
- Optimizing Pipelines for Power and Performance Viji Srinivasan, David Brooks, Michael Gschwind, Pradip Bose,
- Value-Based Clock Gating and Operation Packing: Dynamic Strategies for Improving
- SPATIAL SAMPLING AND REGRESSION STRATEGIES
- Voltage Emergency Prediction: Using Signatures to Reduce Operating Margins
- Impact of Thermal Constraints on Multi-Core Architectures , Benjamin Lee
- REPLACING 6T SRAMS WITH 3T1D DRAMS IN THE L1 DATA CACHE TO
- LATENCY ADAPTATION FOR MULTIPORTED REGISTER FILES TO MITIGATE THE IMPACT OF PROCESS VARIATIONS
- Microarchitecture Parameter Selection To Optimize System Performance Under Process Variation
- Performance, Energy, and Thermal Considerations for SMT and CMP Architectures
- The Design of a Bloom Filter Hardware Accelerator for Ultra Low Power Systems
