- Statistically Optimized Asynchronous Barrel Shifters for Variable Length Codecs \Lambda
- Estimation of Energy Consumption in SpeedIndependent Control Peter A. Beerel and ChengTa Hsieh and Suhrid Wadekar
- [12] T. H. Y. Meng, R. W. Brodersen, and D. G. Messershmitt, ``Automatic Synthesis of Asyn chronous Circuits from HighLevel Specifications'', IEEE Transactions on ComputerAided Design,
- [10] K. Y. Yun and D. L. Dill. Unifying syn chronous/asynchronous state machine synthesis. In
- 6 Conclusions We have given necessary and sufficient conditions under which
- HighPerformance Asynchronous Pipeline Circuits Kenneth Y. Yun \Lambda
- Asynchronous Circuits: An Increasingly Practical Design Solution Peter A. Beerel
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 2, FEBRUARY 2001 217 An Asynchronous Instruction Length Decoder
- TO APPER IN IEEE TRANSACTIONS ON COMPUTERAIDED DESIGN 1 Accelerating Markovian Analysis of Asynchronous
- Efficient State Classification of Finite State Markov Chains y Aiguo Xie and Peter A. Beerel
- BDD MINIMIZATION USING DON'T CARES FOR FORMAL VERIFICATION AND LOGIC SYNTHESIS
- Speculative Completion for the Design of HighPerformance Asynchronous Dynamic Adders
- The Design and Verification of A HighPerformance LowControlOverhead Asynchronous Differential Equation Solver
- Covering Conditions and Algorithms for the Synthesis of SpeedIndependent Circuits
- PERFORMANCE ANALYSIS OF ASYNCHRONOUS CIRCUITS AND A Dissertation Presented to the
- A LowControlOverhead Asynchronous Differential Equation Solver \Lambda
- To appear in ASYNC99, Barcelona, Spain, April 1999 1 Bounding Average Time Separations of Events in Stochastic Timed
- [2] T.A. Chu, Synthesis of SelfTimed VLSI Circuits from Graphtheoretic Specifications, PhD thesis, Massachusetts Institute of Technology, 1987.
- Averagecase optimized technology mapping of onehot domino Weichun Chou \Lambda Peter A. Beerel \Lambda Ran Ginosar yk Rakefet Kol y
- TEMPLATE BASED ASYNCHRONOUS DESIGN Recep Ozgur Ozdag
- LOW-POWER CIRCUIT TECHNIQUES FOR BATTERY-POWERED DSP APPLICATIONS
- Pipeline Optimization for Asynchronous Circuits Sangyun Kim
- This paper presents a back-end design flow for high performance asynchronous ASICs using single-track full-
- A 0.18m IMPLEMENTATION OF A FLOATING-POINT UNIT FOR A PROCESSING-IN-MEMORY SYSTEM
- High-Speed Non-Linear Asynchronous Pipelines Recep O. Ozdag1
- 860 IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. 19, NO. 5, MAY 2001 A Low Latency SISO with Application to Broadband
- MSB-Controlled Inversion Coding for a Low-Power Matrix Transposer
- Relative Timing Based Verification of Timed Circuits and Systems and Peter A. Beerel
- Reducing Probabilistic Timed Petri Nets for Asynchronous Architectural Analysis
- Design of a High-Speed Asynchronous Turbo Decoder Pankaj Golani, Georgios D. Dimou, Mallika Prakash, Peter A. Beerel
- Hazard--Freedom Checking in Speed--Independent Systems ?
- Bounding Average Time Separations of Events in Stochastic Timed Petri Nets with Choice y
- OPTIMIZING AVERAGECASE PERFORMANCE IN THE TECHNOLOGY MAPPING OF ASYNCHRONOUS CIRCUITS
- Sufficient Conditions for Correct GateLevel SpeedIndependent Circuits \Lambda
- Symbolic Reachability Analysis of Large Finite State Machines Using Don't Cares
- Communicating Process Architectures 2005 275 Jan Broenink, Herman Roebbers, Johan Sunter, Peter Welch, and David Wood (Eds.)
- 44 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 1, JANUARY 2000 Sibling-Substitution-Based BDD Minimization Using
- 762 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 5, OCTOBER 2003 Voltage-Pulse Driven Harmonic Resonant Rail
- A heuristic covering technique for optimizing averagecase delay in the technology mapping of asynchronous burstmode circuits
- To appear at ICCAD99 1 Implicit Enumeration of Strongly Connected Components \Lambda
- Estimation and Bounding of Energy Consumption in BurstMode Control Circuits
- Introduction 1.1 Motivation
- Control Circuit Templates for Asynchronous Bundled-Data Pipelines Sunan Tugsinavisut, Peter A. Beerel
- Introduction 1.1 Motivation
- RTL Verification of Timed Asynchronous and Heterogeneous Systems using Symbolic Model Checking
- using a modified version of the Berkeley synthesis system SIS [1]. The complexity of our synthesis tool is polynomial in the
- This paper presents a new fast and templatized family of fine-grain asynchronous pipeline stages based
- The second example was an asynchronous differential equa tion solver that uses timing assumptions to reduce the control
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 10, OCTOBER 2000 1225 V. CONCLUSION
- Hiding Memory Elements in Induced Hierarchical Verification of Speed Independent Circuits *
- IEEE TRANSACTIONS ON VLSI SYSTEMS 1 The Design and Verification of A HighPerformance LowControlOverhead
- Low-Power Sequential Access Memory Design Joong-Seok Moon1
- Advanced clock-delayed1 and self-resetting domino circuits
- HighPerformance TwoPhase Micropipeline Building Blocks: Double EdgeTriggered Latches and BurstMode Select and
- Optimizing averagecase delay in technology mapping of burstmode Peter A. Beerel \Lambda Kenneth Y. Yun y Weichun Chou
- Low Swing Signaling Using a Dynamic Diode-Connected Driver Marcos Ferretti, Peter A. Beerel
