- TPM-SIM: A Framework for Performance Evaluation of Trusted Platform Modules
- 1 supported in part by DARPA through contract number FC 306020020525 under the PACC program, the NSF through award no. MIP 9504767 & EIA 9911099 and IEEC at SUNY Binghamton.
- Appears in the Proceedings of the International Conference on Supercomputing, June, 2002 Low--Complexity Reorder Buffer Architecture
- Exploiting Short-Lived Values for Low-Overhead Transient Fault Recovery
- Performance Evaluation of PDES on Multi-Core Clusters Ketan Bahulkar, Nicole Hofmann, Deepak Jagtap, Nael Abu-Ghazaleh and Dmitry Ponomarev
- SIFT: A Low-Overhead Dynamic Information Flow Tracking Architecture for SMT Processors
- Appears in the Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2003 Reducing Datapath Energy Through the Isolation of ShortLived Operands
- Customized Architectures for Faster Route Finding in GPS-Based Navigation Systems
- Reducing Delay and Power Consumption of the Wakeup Logic through Instruction Packing and Tag Memoization
- AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors*
- * supported in part by DARPA through contract number FC 306020020525 under the PACC program, by the IEEC at SUNYBinghamton and the NSF through award no. MIP 9504767 and EIA 9911099
- Increasing Processor Performance Through Early Register Release Oguz Ergin, Deniz Balkan, Dmitry Ponomarev, Kanad Ghose
- Trade-offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors
- Address-Value Decoupling for Early Register Deallocation Deniz Balkan, Joseph Sharkey, Dmitry Ponomarev
- A CircuitLevel Implementation of Fast, EnergyEfficient CMOS Comparators for HighPerformance Microprocessors
- Adaptive Reorder Buffers for SMT Processors Joseph Sharkey Deniz Balkan Dmitry Ponomarev
- Selective Writeback: Exploiting Transient Values for Energy-Efficiency and Performance
- Register Packing: Exploiting Narrow-Width Operands for Reducing Register File Pressure
- Reducing Power Requirements of Instruction Scheduling Through Dynamic Allocation of Multiple Datapath Resources*
- An L2-Miss-Driven Early Register Deallocation for SMT Processors
- Speculative Avoidance of Register Allocations to Transient Values for Performance and Energy Efficiency
- Appears in the Proceedings of the International Conference on Computer Design (ICCD), 2003 Distributed Reorder Buffer Schemes for Low Power
- Appears in the Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2003 Reducing Reorder Buffer Complexity Through
- Appears in the Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2003 Power Efficient Comparators for Long Arguments in
- Appears in the Proceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation, September, 2002
- ENERGYEFFICIENT INSTRUCTION DISPATCH BUFFER DESIGN FOR SUPERSCALAR PROCESSORS*
- * supported in part by DARPA through contract number FC 306020020525 under the PACC program, by the IEEC at SUNYBinghamton and the NSF through award no. MIP 9504767 and EIA 9911099
- EXPLOITING BITSLICE INACTIVITIES FOR REDUCING ENERGY REQUIREMENTS OF SUPERSCALAR PROCESSORS*
- 1 supported in part by the NSF thru award Nos. EIA 991109, CDA 9700828 & an equipment donation from CISCO Systems
- Non-Monopolizable Caches: Low-Complexity Mitigation of Cache Side Channel Attacks
