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Jerraya, Ahmed Amine - System-Level Synthesis Group, TIMA Laboratory
d'ordre : 106 prsente
On the Parallelism of Convolutional Turbo Decoding and Interleaving Interference
XXII. On the Mechanical Performance of Logical Inference. By W. STANLEY JEVONS, M.A. (Lond.), Professor of Logic, &c. In Owens College, Manchester. Communicated by Professor H. E.
Architectures Logicielles
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1 From Parallelism Levels to a Multi-ASIP Architecture
Butterfly and Benes-Based on-Chip Communication Networks for Multiprocessor Turbo Decoding
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Introduction to Formal Processor Verification at Logic Level : A case Study.
Bandwidth reduction of extrinsic information exchange in turbo decoding
Using Lustre in practical educational activities
Proposition de PostDoc : Modlisation HautNiveau d'une plateforme matrielle ddie des applications de 3D interactive
ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding
