Jantsch, Axel - Department of Microelectronics and Information Technology & School of Information and Communication Technology, Royal Institute of Technology (KTH)

• Adaptively Reconfigurable Controller for the Flash Memory
• On the Roles of Functions and Objects in System Specification
• A Network on Chip Simulator Master of Science Thesis
• P. Stenstrm (Ed.): Transactions on HiPEAC I, LNCS 4050, pp. 239258, 2007. Springer-Verlag Berlin Heidelberg 2007
• A Simple State Transition Control for FSM Programmable Protocol Processors
• FPGA-based Particle Recognition in the HADES Abstract--Modern FPGA technologies are often employed in nuclear and particle physics experimental facilities to accelerate
• Admitting and ejecting flits in wormhole-switched networks on chip
• Andreas Kllkvist Tobias Zetterlund
• Network Layer Communication Performance in Network-on-Chips
• A Low-overhead Fault-aware Deflection Routing Algorithm for 3D Network-on-Chip Chaochao Feng, Minxuan Zhang,
• Mapping Optimisation for Scalable multi-core ARchiTecture: The MOSART approach
• Speedup Analysis of Data-parallel Applications on Multi-core NoCs
• THE ANDRES PROJECT: ANALYSIS AND DESIGN OF RUN-TIME RECONFIGURABLE,
• An analytical approach for dimensioning mixed traffic networks Per Badlund
• Adaptive Power Management for the On-Chip Communication Network
• Towards Performance-oriented Pattern-based Refinement of Synchronous Models onto NoC Communication
• A High Level Power Model for the Nostrum NoC Sandro Penolazzi and Axel Jantsch
• Communicating with Synchronized Environments Tiberiu Seceleanu
• Connection-oriented Multicasting in Wormhole-switched Networks on Chip Zhonghai Lu, Bei Yin and Axel Jantsch
• Evaluation of On-chip Networks Using Deflection Routing Zhonghai Lu
• Refinement of a Perfectly Synchronous Communication Model onto Nostrum NoC Best-Effort Communication Service
• A power efficient flit-admission scheme for wormhole-switched networks on chip Zhonghai Lu, Li Tong, Bei Yin and Axel Jantsch
• Models of Computation in the Design Process Axel Jantsch and Ingo Sander
• On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper
• NoCs: A new Contract between Hardware and Software Axel Jantsch
• Development and Application of Design Transformations in ForSyDe Ingo Sander, Axel Jantsch, and Zhonghai Lu
• Transformation Based Communication and Clock Domain Refinement for System Design
• Controland Com m unication Perform ance Analysis of Em bedded DSP System s in the M ASIC M ethodology
• Heterogeneous System-Level Cosimulation with SDL Per Bjurus*
• A COMPARISON OF SIX LANGUAGES FOR SYSTEM LEVEL DESCRIPTION OF TELECOM
• A Flexible Register Access Control for Programmable Protocol Processors
• MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow
• Network on a Chip: An architecture for billion transistor era Ahmed Hemani1
• Design Automation of Embedded Systems, vol 5, no 1, Kluwer Academic Publisher, February 2000 Functional Validation of Mixed Hardware/Software
• Curriculum Vitae Axel Jantsch
• Transformational System Design Based on a Formal Computational Model and Skeletons
• Master Thesis ELE/ESK/2000-4 Fingerprint identification
• Master Thesis ELE/IMIT/2001-16 Behavioural Modelling of
• EntityEntity EntityEntity Layer N-1 SAP
• Fault Modelling and Error-Control Coding in a Network-on-Chip
• Master Thesis IMIT/LECS 2003-38 With the cooperation of IMEC vzw,
• Master Thesis IMIT/LECS/ 2004 -22 A Study on Power Consumption
• Design and Implementation of the Resource-Network Interface for
• Design and Implementation of a Fat Tree Network on Chip
• Darmstadt University of Technology Department of Electrical Engineering and
• Trading off Power versus Latency using GPLS clocking in 2D-Mesh NoCs
• Modeling of Dynamic Resource Allocation in a Network on Chip
• Implementation of Asynchronous Communication for ForSyDe in Hardware and
• Master Thesis IMIT/LECS/ [2005 -19] Evaluation of Real-time
• Master's Thesis IMIT/LECS/ 2005 89 An Empirical Power Model of the
• Estimation of Power Consumption in Wormhole Routed Networks
• Institut fr Integrierte Systeme Integrated Systems Laboratory
• NNSE: Nostrum Network-on-Chip Simulation Environment Zhonghai Lu, Rikard Thid, Mikael Millberg, Erland Nilsson and Axel Jantsch
• Decimation Filter for the VACS Naresh Vendra & Karthik Chaluvadi
• Load Balancing for Power Minimization
• PANACEA -A case study on the PANACEA NoC -a Nostrum Network on Chip prototype
• Synchronization after Design Refinements with Sensitive Delay Elements
• SoCs for multimedia applications typically use only one port to off-chip DRAM for cost reasons. The sharing of intercon-
• Master Thesis KTH/ICT/LECS-2007-54 Embedded Compression
• Master Thesis IMIT/LECS/ [2007 -53] A study on transactors in multi
• Master Thesis KTH/ ICT / ECS -2007 -88 Hardmotion Design
• Design and Implementation of an FPGA Based Realtime Event Selector for Relativistic
• Design and Analysis of On-Chip Communication for Network-on-Chip
• Modelling Adaptive Systems in ForSyDe1 Ingo Sander 2
• ATCA-BASED COMPUTATION PLATFORM FOR DATA ACQUISITION AND TRIGGERING IN PARTICLE PHYSICS EXPERIMENTS
• A High-end Reconfigurable Computation Platform
• High-Level Debugger Software for Communication-Centric Transaction-Based
• Design Space Exploration Of Field Programmable Counter Arrays
• Correlation and Graphical Presentation of Event Data from a Real-Time System
• Incremental embedded system development based on an RTOS
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 6, JUNE 2008 1091 Application and Verification of Local
• Towards Hierarchical Cluster based Cache Coherence for Large-Scale Network-on-Chip
• Masters Thesis TRITA-ICT-EX-2009:91 Fault-Tolerant Memories in FPGA based
• Theorem Proving Techniques for the Formal Verification of NoC Communications with
• Development of Real Time Scheduler for Master of Science Thesis in System-on-Chip Design
• Run-time Partitioning of Hybrid Distributed Shared Memory on Multi-core Network-on-Chips
• FPGA-based Cherenkov Ring Recognition in Nuclear and Particle Physics Experiments
• Design and Implementation of Dynamic Flow Regulation for On-chip Networks
• Network on Chip Axel Jantsch, Zhonghai Lu, Shashi
• The Nostrum Network on Chip Axel Jantsch, Zhonghai Lu, Mikael
• Slot allocation using logical networks for TDM virtual circuit
• 9:30 State of the art, A. Jantsch 10:00 NoCs in the context of applications and memory
• ForSyDe: A Denotational Framework for Heterogeneous Models of Computation
• Communication Performance in Network-on-Chips Axel Jantsch
• On-Chip Distributed Architectures
• The Nostrum Network on Chip 10 processors
• Networks on Chip Axel Jantsch
• The Nostrum Network on Chip 10 processors
• The Nostrum Network on Chip 10 processors
• Communication Performance in Network-on-Chips Axel Jantsch
• Communication Refinement for a Network-on-Chip Axel Jantsch and Zhonghai Lu
• What is a Good Platform? Axel Jantsch
• Embedded Software/System in the SOC Master Axel Jantsch
• Networks on Chip Shashi Kumar Jonkoping University
• NOC Architecture Axel Jantsch, Royal Institute of Technology, Stockholm
• Institute of M odels ofCom putation in
• E L E C T R O N I C S Y S T E M D E S I G N L A B O R A T O R Y INSTITUTE OF
• Dept. for Speech, Music and Hearing Quarterly Progress and
• Copyright 2007 Society of Photo-Optical Instrumentation Engineers (SPIE). This paper was published at the SPIE conference Infrared Technology and Applications XXXIII, 2007 in Orlando, USA and is made available as an electronic reprint with permission of S
• Simulation and Evaluation for a Network on Chip Architecture Using Ns-2
• A RADIO RESOURCE MANAGEMENT CONCEPT FOR "BUNCHED"
• Supporting Distributed Shared Memory on Multi-core Network-on-Chips Using a Dual Microcoded Controller
• A Simple State Transition Control for FSM Programmable Protocol Processors
• 52 This arTicle has been peer-reviewed. Computing in SCienCe & engineering P e t a s c a l e
• Device Driver and DMA Controller Synthesis from HW/SW Communication Protocol Specifications
• Models of computation and languages for embedded system design
• Custom Microcoded Dynamic Memory Management for Distributed On-Chip Memory Organizations
• NNSE: Nostrum Network-on-Chip Simulation Environment Zhonghai Lu, Rikard Thid, Mikael Millberg, Erland Nilsson and Axel Jantsch
• Institute of System Modelling and
• Compositional Traffic in Networks on Chip Axel Jantsch
• Erlang Capacity Analysis of Multi-access Systems Supporting Voice and Data Services
• Promises and Limitations of 3-D Integration
• Master Thesis KTH/ICT/ECS/ 2008-118 Implementation of a DLI-guard
• Wireless LAN Access Points: Buffer Size Estimation Iyad Al Khatib
• WIRELESS LAN ACCESS POINT MODELING AS A QUEUING SYSTEM Iyad Al Khatib, Gerald Q. Maguire Jr., Rassul Ayani, and Daniel Forsgren
• Performance Analysis of Reconfiguration in Adaptive Real-Time Streaming Applications
• Using Synchronizers for Refining Synchronous Communication onto Hardware/Software Architectures
• Development of Power Models for High Level Power Estimation.
• Bussarkitektur i FPGA system Niklas Molin
• Prototyping Streaming Applications on FPGA Based Chip-Multiprocessor
• Time discrimination in a monotonic, isochronous sequence Anders Friberga)
• Published in IET Computers & Digital Techniques Received on 31st March 2005
• ZURA: "2824_C004" --2005/4/6 --17:26 --page 1 --#1 Models of Embedded
• Reducing FPGA Reconfiguration Time Overhead using Virtual Configurations Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch
• Integrating Software Defined Radio into Wireless Sensor Network
• From Teaching to Learning through Coaching (TLC) Experience from Three Master Level Engineering Courses
• Optimal Regulation of Traffic Flows in Networks-on-Chip
• Special Issue on Networks on Chip Axel Jantsch, Johnny Oberg and Hannu Tenhunen
• Hardware/Software Co-design of an ATCA-based Computation Platform for Data Acquisition and
• Networks on Chip 10 processors
• Arnau Ferr Ciur Stockholm, April 2002
• Area and Performance Optimization of Barrier Synchronization on Multi-core Network-on-Chips
• Performance Analysis with Confidence Intervals for Embedded Software Processes
• Master Thesis KTH/ICT/ECS/ 2008-98 Implementation of Message
• Prototyping of a Memory Subsystem on FPGA to interface to Flash memories
• Power Analysis of Link Level and End-to-end Protection in Networks on Chip
• Design of a Power Saving Methodology for Next Generation
• SLDL Workshop, September 1998 Comparison of Six Languages for System Level
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 12, DECEMBER 2010 1973 Buffer Optimization in Network-on-Chip Through
• Resource Allocation for Quality of Service On-chip Communication
• Memory Architecture and Management in a NoC Platform
• Networks on Chip Axel Jantsch
• The Nostrum Network on Chip 10 processors
• FP6-2004-IST-4 Open SoC Design Platform for Reuse and Inte-
• Dept. for Speech, Music and Hearing Quarterly Progress and
• A Flexible Register Access Control for Programmable Protocol Processors
• Master Thesis TRITA-ICT-EX-2010:103 A New Approach For Codec
• A Network-based System Architecture for Remote Medical Applications
• A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uni-
• A Radio-Frequency and Body-Coupled Communication Dual Technology Wire-
• A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis: ECG
• Will Networks on Chip Close the Productivity Gap? Axel Jantsch
• Extending Platform-Based Design to Network on Chip Systems Juha-Pekka Soininen1
• Master Thesis KTH/ICT/ECS -2007-55 Applications onto
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 1, JANUARY 2004 17 System Modeling and Transformational
• The composite signal flow model of computation targets systems with significant control and data processing parts.
• Network-on-Chips Fudan University, Shanghai, June 2009
• Memory Architecture and Management in an NoC Platform Axel Jantsch, Xiaowen Chen, Abdul Naeem, Yuang Zhang, Sandro Penolazzi and Zhonghai Lu
• A Flow Regulator for On-Chip Communication Zhonghai Lu, Dimitris Brachos and Axel Jantsch
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, TVLSI-00078-2007.R1 1 TDM Virtual-Circuit Configuration for
• Institute of Electronic Design Automation-
• Abstract--Measuring and comparing performance, cost, and other features of advanced communication architectures for
• Vital Signs Acquisition and Communication System Board Implementation
• Design and Implementation of Navigation Controller
• Trends of Terascale Computing Chips in the Next Ten Years
• DYNAMIC LINK ASYMMETRY IN `BUNCHED' WIRELESS Magnus Lindstrm & Jens Zander
• Simulation and Performance Evaluation for Networks on Chip
• Models of Computation for Networks on Chip Axel Jantsch
• Erlang Capacity of Multi-Access Systems with Service-based Access Selection
• Flow Regulation for On-Chip Communication Zhonghai Lu, Mikael Millberg, Axel Jantsch
• Memory Architecture and Management in a NoC Platform
• The Nostrum Network on Chip NI Axel Jantsch, Zhonghai Lu, Shashi
• EWD: A Metamodeling Driven Customizable Multi-MoC System Modeling Framework
• 2.1 Introduction Due to their compact geometry, 3-D integrated systems hold promises to signifi-
• Abstract-This paper investigates four different short circuit fault conditions which can occur for an inverter-fed perma-
• ANDRES -ANalysis and Design of run-time REconfigurable, heterogeneous Systems
• Simulation and Performance Evaluation for Networks on Chip
• Energy-Aware Task Allocation for Network-on-Chip Architectures
• A Multiprocessor System-on-Chip for Real-Time Biomedical Monitoring and Analysis
• Structural Communication Anders Friberg and Giovanni Umberto Battel
• Trigger Algorithm Development on FPGA-based Compute Nodes
• Wireless Network-on-Chips as Autonomous Systems: A Novel Solution for Biomedical Healthcare and Space Exploration Sensor-Networks
• HetMoC: Heterogeneous Modelling in SystemC Jun Zhu, Ingo Sander, Axel Jantsch
• The Nostrum Network on Chip Axel Jantsch
• Tutorial: Networks on Chip The 1st ACM/IEEE International Symposium on Networks-on-Chip
• Master Thesis KTH/ ICT / ECS -2007 -123 System-level power management design
• Networks on Chip: A New Contract between
• Software Development for a Mobile Projector Master Thesis
• Master Thesis ICT/ECS-2006-137 Integration of ISS Simulation
• Feasibility Analysis of Messages for On-chip Networks Using Wormhole Routing Zhonghai Lu, Axel Jantsch and Ingo Sander
• Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications
• This paper describes a technique called producer-push that enhances the performance of a page-based software
• Master Thesis at Electronics Systems Master Thesis at Department of Electronics Systems
• Resource Allocation for QoS On-Chip Communication Axel Jantsch and Zhonghai Lu
• Master Thesis IMIT/LECS-2004-72 Implementation and Evaluation of Segmented-Bus
• Curriculum Vitae Axel Jantsch
• Axel Jantsch Professor at Royal Institute of Technology (KTH)
• The Nostrum Network on Chip 10 processors
• A study of NoC Exit Strategies Mikael Millberg & Axel Jantsch
• AMBA Bus Emulation in the Nostrum NoC using Best Effort Communication
• Masters Thesis TRITAICTEX2009:11 An Authentication Framework
• 1 of 9Submitted to IEEE Design & Test of Computers (22 March 2000 4:59 pm) Abstract: We propose a conceptual framework, called the Rugby Model, in which designs, design processes
• Multi-FPGA Implementation of a Network-on-Chip Based Many-core Architecture with Fast Barrier
• Development environment for single chip computers intended for
• ICT/ECS-2008-41 Generalization of Slot Table Size for Virtual
• Flit Admission in On-chip Wormhole-switched Networks with Virtual Channels Zhonghai Lu and Axel Jantsch
• FON: FAULT-ON-NEIGHBOR AWARE ROUTING ALGORITHM FOR NETWORKS-ON-CHIP
• Scalability of Network-on-Chip Communication Architecture for 3-D Meshes Awet Yemane Weldezion
• Communication Performance in Network-on-Chips Axel Jantsch
• Scalability of Weak Consistency in NoC based Multicore Architectures
• Master Thesis IMIT/LECS/ [2005 -71] Design of Frequency Controller
• Re nement of a System Speci cation for a Digital Equalizer into HW and SW Implementations
• Analytical Evaluation of Retransmission Schemes in Wireless Sensor Networks
• CORDIC IP Block Design Vitaliy Kuhar
• A Reconfigurable Fault-tolerant Deflection Routing Algorithm Based on Reinforcement Learning for
• A Worst Case performance model for TDM Virtual Circuit in NoCs
• Cache misses due to coherence actions are often the major source for performance degradation in cache coherent multiprocessors. It
• Even though shared memory multiprocessors are becoming more and more common, it is still a formidable task to achieve high
• Parallel programs that use critical sections and are executed on a shared-memory multiprocessor with a write-
• Cache misses due to coherence and directory maintenance is a major reason for poor performance in shared memory
• Improving the Performance of a Wormhole Router and Wormhole Flow Control
• Fundamenta Informaticae XX (2008) 127 1 Modeling Communication with Synchronized Environments
• Realization and Performance Comparison of Sequential and Weak Memory Consistency Models in Network-on-Chip based Multi-core Systems
• When designing a network the use of buffers is inevitable. Buffers are used at the entry point, inside
• MPSoC ECG Biochip: A Multiprocessor System-on-Chip for Real-Time Human Heart Monitoring and Analysis
• A Network on Chip Architecture and Design Methodology Shashi Kumar1
• Load distribution with the Proximity Congestion Awareness in a Network on Chip
• Handling Shared Variable Synchronization in Multi-core Network-on-Chips with Distributed Memory
• Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique
• A Comparative Characterization of Communication Patterns in Applications using
• Network-on-Chip Micro-Benchmarks Zhonghai Lu *, Axel Jantsch *, Erno Salminen and Cristian Grecu
• SML-Sys: A Functional Framework with Multiple Models of Computation for Modeling Heterogeneous System
• System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments
• Guaranteed Bandwidth using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip
• Network-Calculus-based Performance Analysis for Wireless Sensor
• High-Level Estimation and Trade-Off Analysis for Adaptive Real-Time Systems Ingo Sander, Jun Zhu, Axel Jantsch
• Implementation of a 2x2 NoC with Wishbone Daniel kerlund
• FPGA-based Adaptive Computing for Correlated Multi-stream Processing
• Performance Analysis and Design Space Exploration for High-End Biomedical Applications
• Sting Bluetooth Control (SBC) via Motorola HT820
• Flexible Bus and NoC Performance Analysis with Configurable Synthetic Rikard Thid, Ingo Sander, Axel Jantsch
• UMTS Gi Interfacing and Measuring System
• Inter-Process Communication using Pipes in FPGA-based Adaptive Computing Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch
• KTH/ICT/ECS-2009-7 INVESTIGATION OF A/D CONVERTERS FOR IMPLANTABLE
• 2nd ICES Annual Conference, 2009-09-02 Trends in Terascale
• RUN-TIME PARTIAL RECONFIGURATION SPEED INVESTIGATION AND ARCHITECTURAL DESIGN SPACE EXPLORATION
• Hardware/Software Co-design of a General-Purpose Computation Platform in Particle Physics
• Simulated Annealing Techniques for Mapping Cores onto 2-D Mesh
• SDF to Synchronous Cross Domain Analysis in ForSyDe Stream Processing Framework
• Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip
• Flit Ejection in On-chip Wormhole-switched Networks with Virtual Channels Zhonghai Lu and Axel Jantsch
• Master Thesis ICT/ECS 2007 19 High Precision Motor and Servo
• The Usage of Stochastic Processes in Embedded System Specifications
• Layered Switching for Networks on Chip Zhonghai Lu
• Pareto Efficient Design for Reconfigurable Streaming Applications on CPU/FPGAs
• A Synchronization Algorithm for Local Temporal Refinements in Perfectly Synchronous Models with Nested
• Implementation of a JPEG Encoder on Nostrum
• Realization and Scalability of Release and Protected Release Consistency Models in NoC based Systems
• Directory-based, write-invalidate cache coherence proto-cols are effective in reducing latencies to the memory but
• REFINING SYNCHRONOUS COMMUNICATION ONTO NETWORK-ON-CHIP BEST-EFFORT SERVICES
• Deterministic Worst-case Performance Analysis for Wireless Sensor Networks
• Development and Evaluation of a Memory Consistency and Cache Coherence
• Scalability of Relaxed Consistency Models in NoC based Multicore Architectures
• Energy Efficient Streaming Applications with Guaranteed Throughput on MPSoCs
• The Nostrum Backbone -a Communication Protocol Stack for Networks on Chip Mikael Millberg, Erland Nilsson, Rikard Thid, Shashi Kumar and Axel Jantsch
• Slot Allocation Using Logical Networks for TDM Virtual-Circuit Configuration for Network-on-Chip
• Digital Filters for Bio-Signal Processing in the VACS Platform
• Evaluating NoC communication backbones with simulation Rikard Thid, Mikael Millberg, and Axel Jantsch
• http://www.ac-psych.org Overview of the KTH rule system for musical
• MASTER THESIS TRITA-ICT-EX-2010:104 A Prototype of a Wireless 2-D
• The MOSART Mapping Optimization for multi-core ARchiTectures
• Optimal Network Architectures for Minimizing Average Distance in k-ary n-dimensional Mesh Networks
• WILL NETWORKS ON CHIP CLOSE THE PRODUCTIVITY GAP?
• Low-Power and Error Coding for Network-on-Chip Traffic
• Master Thesis IMIT/LECS/2007-63 Implementation of
• Master Thesis ICT/ECS [2008 076] Integration of Mathworks
• Accesses to the shared memory remain to be a major performance limitation in shared memory multiprocessors.
• A Framework for Designing Congestion-Aware Deterministic Routing
• KTH/ICT/ECS-2007-32 Implementation of Re-configurable Analog Circuitry on Field Programmable Analog
• Models of Computation for Networks on Chip Axel Jantsch
• Traffic Splitting with Network Calculus for Mesh Sensor Networks Huimin She, Zhonghai Lu, Axel Jantsch, Li-Rong Zheng, Dian Zhou
• ERROR-TOLERANT INTERCONNECT SCHEMES Heiko Zimmer
• In J. Sundberg & B. Brunson (Eds.) Proceedings of Music and Music Science, Stockholm, October 28-A fuzzy analyzer of emotional expression in music
• Traffic Configuration for Evaluating Networks on Chips Zhonghai Lu and Axel Jantsch
• Power analysis of link level and end-to-end data protection in networks on chip
• Master Thesis ICT/ECS-2006-71 Multi-IP-Based SoC Design Including CCM
• A Programmable Protocol Processor Architecture for High Speed Internet Protocol Processing
• Abstract -In this paper we introduce Priority Based Forced Requeue to decrease worst-case latencies in NoCs offering best
• Schematic Design of an FPGA-Based Network-on-board
• Constrained Global Scheduling of Streaming Applications on MPSoCs Jun Zhu, Ingo Sander, Axel Jantsch
• Evaluation of Deflection-routed On-Chip Networks
• Simulation and evaluation of multicast implementations
• Master Thesis IMIT/LECS/2002-25 Performance Estimation in ForSyDe
• Power-efficient Tree-based Multicast Support for Networks-on-Chip Wenmin Hu1,2
• Hardware Design and Synthesis in ForSyDe Ingo Sander, Alfonso Acosta, and Axel Jantsch
• TRITA-ICT-EX-2009:157 Master Thesis in Electronic System Design
• Buffer Minimization of Real-Time Streaming Applications Scheduling on Hybrid CPU/FPGA Architectures
• Design and Implementation of a Multi Channel Circuit-Switched Network-on-Chip
• Network-on-Chip Multicasting with Low Latency Path Setup
• Evaluation of Deflection Routing on Various NoC Topologies Chaochao Feng1,2*
• ForSyDe: A Formal Framework for Heterogeneous Models of Computation
• Parallel Computing based on GPGPU using Compute Unified
• 3-D Integration and the Limits of Silicon Computation Dinesh Pamunuwa
• 978-3-9810801-8-6/DATE12/2012 EDAA Parallel Probing: Dynamic and Constant Time Setup
• ForSyDe: A Formal Framework for Heterogeneous Models of Computation
• * now at Agency for Science, Technology and Research (A*STAR), Singapore Axel Jantsch
• Shared Memory in Multiprocessors
• Output Process of Variable Bit-Rate Flows in On-chip Networks Based on Aggregate Scheduling
• Architectural Techniques for Improving Performance in Networks on Chip
• This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
• 978-3-9810801-8-6/DATE12/2012 EDAA Parallel Probing: Dynamic and Constant Time Setup
• Concept and Design of Exhaustive-Parallel search algorithm for Network-on-Chip
• Dear Editors and Reviewers, This is the authors' reply to the paper (2011XCL7077) entitled "Self-selection pseudo-circuit: a
• A study on the usage of a micro-controller versus custom hardware
• IEICE TRANS. INF. & SYST., VOL.Exx??, NO.xx XXXX 201x Support Efficient and Fault-tolerant Multicast in Bufferless
• SELF-ADAPTIVE NOC POWER MANAGEMENT WITH DUAL-LEVEL AGENTS: ARCHITECTURE AND
• IEICE TRANS. INF. & SYST., VOL.Exx??, NO.xx XXXX 200x A 1-cycle 1.25GHz Bufferless Router for 3D Network-on-Chip
• Worst-Case Delay Analysis of Variable Bit-Rate Flows in Network-on-Chip with Aggregate Scheduling