- Publications from the Uppsala Architecture Re-search Team (UART)
- UPTEC F 02 096 Simple and Efficient Instrumentation
- ISBN 91-7170-103-6 ISRN SICS D--8--SE Toward Scalable
- Skewed Caches from a Low-Power Perspective Mathias Spjuth, Martin Karlsson and Erik Hagersten
- A Statistical Multiprocessor Cache Model Erik Berg, Hakan Zeffer and Erik Hagersten
- Removing the Overhead from Software-Based Shared Memory
- Figure 1: WildFire connects up to four E6000 by inserting one WildFire Interface Board (WFI) in each node.
- From the 18th International Symposium on Computer Architecture, 1991 Race-free Interconnection Networks
- VASA: A SIMULATOR INFRASTRUCTURE WITH ADJUSTABLE FIDELITY Dan Wallin, Hakan Zeffer, Martin Karlsson and Erik Hagersten
- Exploiting Spatial Store Locality through Permission Caching in Software DSMs
- Message off the critical path
- SIP: Performance Tuning through Source Code Interdependence
- A Case For Low-Complexity Multi-CMP Architectures Hakan Zeffer and Erik Hagersten
- TMA: A Trap-Based Memory Architecture Hakan Zeffer, Zoran Radovic, Martin Karlsson and Erik Hagersten
- Exploring Processor Design Options for Java-Based Middleware Martin Karlsson and Erik Hagersten
- StatCache: A Probabilistic Approach to Efficient and Accurate Data Locality Analysis
- Miss Penalty Reduction Using Bundled Capacity Prefetching in Multiprocessors Dan Wallin and Erik Hagersten
- Performance of PDE Solvers on a Self-Optimizing NUMA Architecture
- Efficient Synchronization for Nonuniform Communication Architectures
- RH Lock: A Scalable Hierarchical Spin Lock Zoran Radovic and Erik Hagersten
- Performance of High-Accuracy PDE Solvers on a Self-Optimizing NUMA Architecture
- Simulation-Based Debugging of Soft Real-Time Applications Lars Albertsson
- DSZOOM Low Latency Software-Based Shared Memory
- To appear in IEEE PROCEEDINGS on Distributed Shared-Memory Multiprocessors Mar. 1999 Parallel Computing in the Commercial Marketplace. Rev 4 Nov 20 1998 1
- GigaplaneTM: A High Performance Bus for Large SMPs July 16, 1996 5.0 Summary
- Queue Locks on Cache Coherent Multiprocessors Peter Magnusson Anders Landin
- Hag92 E. Hagersten. Toward Scalable Cache Only Memory Architectures. PhD thesis, Royal Institute of Technology, Stockholm Swedish Institute of Com-
- Bundling: Reducing the Overhead of Multiprocessor Prefetchers Dan Wallin and Erik Hagersten
- IT Master theses UPTEC F 00 093
- Publications from the Uppsala Architecture Re search Team (UART)
- This work is supported in part by the National Science Founda-tion, with grants EIA-9971256, EIA-0205286, and CDA-
- Fast Data-Locality Profiling of Native Execution Erik Berg and Erik Hagersten
- Hierarchical Backoff Locks for Nonuniform Communication Architectures Zoran Radovic and Erik Hagersten
- Simple COMA Node Implementations Erik Hagersten Ashley Saulsbury and Anders Landin
- Using Complete System Simulation for Temporal Debugging of General Purpose Operating Systems and Workloads
- Implementing Low Latency Distributed Software-Based Shared Memory
