- A Multi-Pronged Approach to Benchmark Characterization Nikola Puzovic, Sally A. McKee, Revital Eres, Ayal Zaks, Paolo Gai, Stephan Wong, and Roberto Giorgi
- Exploiting Locality to Improve Leakage Reduction in Embedded Drowsy I-Caches at Same Area/Speed
- University of Siena Faculty of Engineering Blue Sign Translator
- Dipartimento di Ingegneria dell'Informazione Universit degli Studi di Siena
- Exploiting Parallelism of Deblocking Filter of H.264 on DTA architecture
- Core Design and Scalability of Tiled SDF Architecture
- Int. J. High Performance Computing and Networking, Vol. 1, Nos. 1/2/3, 2004 17 Copyright 2004 Inderscience Enterprises Ltd.
- Execution and Cache Performance of the Scheduled Dataflow Architecture
- Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on
- Filtering drowsy instruction cache to achieve better efficiency
- Instruction Set Extensions for Cryptographic Applications
- A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields
- Sistema per la traduzione in Lingua Italiana dei Segni Blue Sign Translator / Wireless Sign System
- Memory Performance of Public-Key Cryptography Methods in Mobile Environments
- Scheduling and NoC Traffic Reduction in T-SDF Architecture
- Cache Memory Design for Embedded Systems Based on Program Locality Analysis
- An Educational Environment for Designing and Performance Tuning of
- Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation
- Adaptive cache decay Paolo Bennati, Roberto Giorgi
- ACACES 2005 Poster abstracts 47 Recent Proposals for Tiled Architectures
- Comparing Execution Performance of Scheduled Dataflow With RISC Processors Krishna M. Kavi
- An approach for investigating design and tuning performance of embedded systems
- ACACES 2005 Poster abstracts 133 New techniques for low power caches
- Reducing Leakage through Filter Cache Roberto Giorgi
- Parallel Architecture and Compilation Techniques: Selection of Workshop Papers,
- Boosting the Performance of Three-Tier Web Servers
- PERFORMANCE ANALYSIS OF ELECTRONIC COMMERCE MULTIPROCESSOR SERVER
- JCacheSim: simulatore visuale di gerarchia di memoria con interprete per programmi MIPS
- Web-based training on computer architecture: The case for JCachesim Irina Branovic1
- Decoupled Threaded Architecture Roberto Giorgi, Zdravko Popovic, Nikola Puzovic1
- BLUESIGN: traduttore multimediale portatile per non udenti Sandro Bartolini, Paolo Bennati, Roberto Giorgi
- 29. A Coherence Protocol for the Elimination of Passive Sharing in Single and Multiple Threaded Shared-Bus
- 1. INTRODUZIONE La sordit grave e/o profonda, da qualsia-
- MEmory performance: DEaling with Applications, systems and architecture
- Journal of Embedded Computing, Volume 2, Number 2 137 Guest-editorial
- Reducing Coherence Overhead and Boosting Performance of High-End SMP Multiprocessors Running a DSS Workload
- A Workload Characterization of Elliptic Curve Cryptography Methods in Embedded Environments
- Simulation study of memory performance of SMP multiprocessors running a TPC-W workload
- Trace Factory Generating Workloads for Trace-Driven Simulation
- Some Considerations About Passive Sharing in Shared-Memory Multiprocessors
- Proceedings of HiPEAC Workshop on
- TERAFLUX: Ideas for the Future Many-Cores Roberto Giorgi
- Programming Abstractions and Toolchain for Dataflow Multithreading Architectures
- Implementing Fine/Medium Grained TLP Support in a Many-Core Architecture
- Abstract--The focus of our study is the support for fine/medium grained Thread Level Parallelism (TLP) by using a
- Implementing DTA support in CellSim Roberto Giorgi1,3, Nikola Puzovic2,3, Zdravko Popovic2,3
- DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems Roberto Giorgi, Zdravko Popovic, Nikola Puzovic
- Reducing leakage in power-saving capable caches for embedded systems by using a filter cache
- Elliptic Curve Cryptography support for ARM based Embedded systems
- Il sistema Bluesign-2 stato realizzato su un computer palmare, sfruttando la pos-
- WebMIPS: A New Web-Based MIPS Simulation Environment for Computer Architecture Education
- Speeding-up Multiprocessors Running DSS Workloads through Coherence Protocols
- Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications
- Accelerating DSS Workloads through Coherence Protocols Pierfrancesco Foglia, Cosimo Antonio Prete
- EVALUATING OPTIMIZATIONS FOR MULTIPROCESSORS E-COMMERCE SERVER
- Process Migration Effects on Memory Performance of Multiprocessor Web-Servers
- An Educational Environment for Designing and Performance Tuning of Embedded Systems
- Analysis of sharing overhead in Shared Memory Multiprocessors Pierfrancesco Foglia, Roberto Giorgi and Cosimo Antonio Prete
- An Educational Environment for Program Behavior Analysis and Cache Memory Design
- BUS UTILIZATION ANALYSIS OF MULTITHREADED SHARED-BUS MULTIPROCESSORS: INITIAL RESULTS
- A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors
- Evaluation of a Coherence Protocol for Eliminating Passive Sharing
- Universit degli Studi di Pisa Facolt di Ingegneria
- PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus
- Analyzing Scalability of Deblocking Filter of H.264 via TLP exploitation in a new many-core architecture
- A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors
- Exploiting DMA to enable non-blocking execution in Decoupled Threaded Architecture
- A Case Study on the Design Trade-off of a Thread Level Data Flow based Many-core Architecture
- T-Star (T*): An x86-64 ISA Extension to support thread execution on many cores
- Early Results from ERA Embedded Reconfigurable Architectures
- Characterizing Phase Behavior for Dynamically Reconfigurable Architectures
- A Fault Detection and Recovery Architecture for a Teradevice Dataflow System
- 239J.M.P. Cardoso and M. Hbner (eds.), Reconfigurable Computing: From FPGAs to Hardware/Software Codesign, DOI 10.1007/978-1-4614-0061-5_10,
- Architectural Simulation in the Kilo-core Era University of Siena
- Simulating the Future kilo-x86-64 core Processors and their Infrastructure Antoni Portero1, Alberto Scionti1, Zhibin Yu1, Paolo Faraboschi2, Caroline Concatto3, Luigi Carro3, Arne Garbade4,
- Available online at www.sciencedirect.com Procedia Computer Science 7 (2011) 146147
