- FLEXIBLE RECONFIGURABLE MULTIPLIER BLOCKS SUITABLE FOR ENHANCING THE ARCHITECTURE OF FPGAs
- Pipeline Morphing and Virtual Pipelines W. Luk, N. Shirazi, S.R. Guo and P.Y.K. Cheung
- 0018-9162/00/$10.00 2000 IEEE50 Computer Video Image
- Published in IEEE FPGA Custom Computing Machine Conference, 2002. (b) an example computation graph
- Synthia: Synthesis of Interacting Automata targeting LUT-based FPGAs
- Recon gurable Computing for Augmented Reality W. Luk, T.K. Lee and J.R. Rice
- Reconfigurable Shape-Adaptive Template Matching Architectures Jrn Gause1
- Framework and Tools for Run-Time Recon gurable Designs
- A Structured Methodology for System-on-an-FPGA Design
- BIST Based Interconnect Fault Location for Nicola Campregher1
- A novel implementation of tile-based address mapping Sambuddhi Hettiaratchi and Peter Y.K. Cheung
- Non-uniform Segmentation for Hardware Function Evaluation
- Multiple Restricted Multiplication Nalin Sidahao, George A. Constantinides, and Peter Y.K. Cheung
- PTM: A Technology Mapper for Pass-Transistor Logic Nan Zhuang, Marcus v. Scotti and Peter Y.K. Cheung1
- Compilation Tools for Run-Time Recon gurable Designs Wayne Luk and Nabeel Shirazi
- On the Viability of FPGA-based Integrated Coprocessors Osama T. Albaharna
- A Hardware Gaussian Noise Generator for Channel Code Evaluation Dong-U Lee and Wayne Luk
- Simon Haynes, Peter Cheung A Joint project between
- Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation
- Guest Editors' Introduction: Field Programmable Logic and Applications
- Automating Production of Run-Time Recon gurable Designs Nabeel Shirazi and Wayne Luk
- Modelling and Optimising Run-Time Reconfigurable Systems Wayne Luk and Nabeel Shirazi
- Ratiometric current-mode rational DAC C.T.Y. Sim, C. Toumazou and P.Y.K. Cheung
- Run-Time Management of Dynamically Recon gurable Designs
- A Steerable Complex Wavelet Construction and Its Implementation on FPGA
- AUTONOMOUS MEMORY BLOCK FOR RECONFIGURABLE COMPUTING Wim J. C. Melis, Peter Y. K. Cheung
- SoftSONIC: A Customisable Modular Platform for Video Applications
- Globally Asynchronous Locally Synchronous FPGA Architectures
- Mesh Partitioning Approach to Energy Efficient Data Layout Sambuddhi Hettiaratchi Peter Y.K. Cheung
- Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
- Heuristic Datapath Allocation for Multiple Wordlength Systems George A. Constantinides, Peter Y.K. Cheung
- ELECTRONICS LETTERS 17th August 2000 Vol. 36 No. 17 Optimal datapath allocation for multiple-
- ELECTRONICS LETTERS 6th January 2000 Vol. 36 No. 1 Optimisation of full-custom logic cells using
- ELECTRONICS LETTERS 11th November 1999 Vol. 35 No. 23 Truncation noise in fixed-point SFGs
- Submitted to FPL'99 SONIC -A Plug-In Architecture for Video Processing
- Riley-2: A Flexible Platform for Codesign and Dynamic Reconfigurable Computing Research
- Quasi-Delay Insensitive Bus for Fully Asynchronous Systems
- Adaptive Automatic Facial Feature Segmentation Hasan Demirel Thomas J. Clarke Peter Y.K. Cheung
- 1432 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 10, OCTOBER 2003 Wordlength Optimization for Linear Digital
