Hu, Jiang - Department of Electrical and Computer Engineering, Texas A&M University

• Pattern Sensitive Placement For Manufacturability Department of ECE
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 1, JANUARY 2002 3 Buffered Steiner Trees for Difficult Instances
• Applications of Network Coding in Global Routing Nikhil Nemade, Alex Sprintson, and Jiang Hu
• Physical Design Techniques for Optimizing RTA-induced Variations
• Skew Scheduling and Clock Routing for Improved Tolerance to Process Variations Ganesh Venkataraman, C. N. Sze and Jiang Hu
• Steiner Network Construction for Timing Critical Nets Shiyan Hu, Qiuyang Li, Jiang Hu and Peng Li
• Fast Decap Allocation Based on Algebraic Multigrid Cheng Zhuo, Jiang Hu1
• Making Fast Buffer Insertion Even Faster Via Approximation Techniques , C. N. Sze1
• Optimizations in VLSI Designs: Floorplanning, Timing and Layout D.Z. Du and B. Lu (Eds.) pp. -- --
• A Simple Yet Effective Merging Scheme for PrescribedSkew Clock Routing
• Practical Techniques to Reduce Skew and Its Variations in Buffered Clock Networks
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 2, FEBRUARY 2010 223 A New Algorithm for Simultaneous Gate Sizing
• 1002 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 6, JUNE 2010 the range of lower costs, the k-NN and MC curves practically coin-
• 436 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 4, APRIL 1999 Non-Hanan Routing
• Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment
• Congestion-driven Codesign of Power and Signal Sachin S. Sapatnekar
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 2, FEBRUARY 2007 149 Integrated Placement and Skew Optimization
• Handling Partial Correlations in Yield Prediction Sridhar Varadan Janet Wang Jiang Hu
• Accurate Clock Mesh Sizing via Sequential Quadratic Programming
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 1, JANUARY 2010 131 Combinatorial Algorithms for Fast Clock
• Analytical Bound for Unwanted Clock Skew due to Wire Width Variation Anand Rajaram , Bing Lu, Wei Guo, Rabi Mahapatra
• A Timing-constrained Algorithm for Simultaneous Global Routing of Multiple Nets
• Path Based Buffer Insertion C. N. Sze, Charles J. Alpert, Jiang Hu and Weiping Shi
• Planar-CRX: A Single-Layer Zero Skew Clock Routing in X-architecture Weixiang Shen, Yici Cai, Xianlong Hong
• Combinatorial Algorithms for Fast Clock Mesh Optimization
• Statistical Clock Tree Routing for Robustness to Process Variations
• Porosity Aware Buffered Steiner Tree Construction Charles J. Alpert
• An Efficient Algorithm For RLC Buffer Insertion Zhanyuan Jiang, Shiyan Hu, Jiang Hu and Weiping Shi
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 10, OCTOBER 2007 1067 Utilizing Redundancy for Timing
• Bu er Insertion with Adaptive Blockage Avoidance Department of Electrical Engineering
• 136 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 1, JANUARY 2004 [4] B. Krauter, S. Mehrotra, and V. Chandramouli, "Including inductive ef-
• FAR-DS: Full-plane AWE Routing with Driver Sizing Jiang Hu and Sachin S. Sapatnekar
• GPU-Based Parallelization for Fast Circuit Optimization Department of ECE
• Reducing Clock Skew Variability via Cross Links Anand Rajaram
• Buffer insertion has become an increasingly critical optimi-zation in high performance design. The problem of finding a
• SAT Based Multi-Net Rip-up-and-Reroute for Manufacturing Hotspot Removal
• DiCER: Distributed and Cost-Effective Redundancy for Variation Tolerance
• Integrated Placement and Skew Optimization for Rotary Clocking
• Buffered Clock Tree for High Quality IC Design Rishi Chaturvedi and Jiang Hu
• A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment
• Buffer Insertion with Adaptive Blockage Avoidance [Extended Abstract]
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 12, DECEMBER 2008 2183 Buffering Interconnect for Multicore
• Multi-Scenario Buffer Insertion in Multi-Core Processor Department of ECE
• 446 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 4, APRIL 2000 Algorithms for Non-Hanan-Based Optimization for
• 556 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUTS AND SYSTEMS, VOL. 20, NO. 4, APRIL 2001 Short Papers_______________________________________________________________________________
• Steiner node attractive force repulsive force circular force
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 9, SEPTEMBER 2002 1025 A Timing-Constrained Simultaneous Global Routing
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH 2003 100 Porosity Aware Buffered Steiner Tree Construction
• 734 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 4, APRIL 2006 Short Papers
• 1140 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006 D. J. Frank, D. V. Singh, G. M. Cohen, S. V. Nitta, D. C. Boyd,
• 1176 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 6, JUNE 2006 Reducing Clock Skew Variability via Crosslinks
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006 1869 Analytical Bound for Unwanted Clock Skew
• 1332 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 15, NO. 12, DECEMBER 2007 Wire Sizing and Spacing for Lithographic
• 738 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 4, APRIL 2008 Power Grid Analysis and Optimization
• 818 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 6, JUNE 2009 Gate Sizing for Cell-Library-Based Designs
• 770 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 17, NO. 6, JUNE 2009 Clock Buffer Polarity Assignment for
• Layer Assignment for Crosstalk Risk Minimization Di Wu , Jiang Hu
• Layout modification for library cell Alt-PSM composability Ke Cao, Jiang Hu, Mosong Cheng
• Buffer insertion is an increasingly critical optimization for achieving timing closure, and the number of buffers required
• Closed formed expressions for buffered interconnect delay approximation have been around for some time. However,
• Exploiting Level Sensitive Latches in Wire Pipelining Vikram Seth
• Clock Network Minimization Methodology Based On Incremental Placement Liang Huang, Yici Cai, Qiang Zhou, Xianlong Hong, Jiang Hu*, Yongqiang Lu
• Register Placement for Low Power Clock Network* Yongqiang Lua
• Improved Algorithms for Link-Based Non-Tree Clock Networks for Skew Variability Reduction
• Associative Skew Clock Routing for Difficult Instances Min-Seok Kim
• An Improved AMG-based Method for Fast Power Grid Analysis Cheng Zhuo, Jiang Hu1
• Efficient Model Update for General Link-Insertion Department of ECE
• An Optimal Jumper Insertion Algorithm for Antenna Avoidance/Fixing on General Routing Trees with Obstacles
• High Performance Clock Routing in X-architecture Weixiang Shenia, Yici Caia, Jiang Hub, Xianlong Honga, Bing Luc
• Standard Cell Characterization Considering Lithography Induced Variations
• A New RLC Buffer Insertion Algorithm Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li
• A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
• Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders
• Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction
• Modeling, Optimization and Control of Rotary Traveling-Wave Cheng Zhuo, Huafeng Zhang, Rupak Samanta1
• Analysis of Large Clock Meshes Via Harmonic-Weighted Model Order Reduction and Port Sliding
• A New Fast Slew Buffering Algorithm Without Input Slew Assumptions
• Low Power Clock Buffer Planning Methodology in F-D Placement for Large Scale Circuit Design
• Elastic Timing Scheme for Energy-Efficient and Robust Performance
• Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
• Discrete Buffer and Wire Sizing for Link-based Non-tree Clock Networks
• Activity and Register Placement Aware Gated Clock Network Design
• Delay-Optimal Simultaneous Technology Mapping and Placement with Applications
• Impact of Lithography-friendly Circuit Layout Pratik Shah
• Efficient Rerouting Algorithms for Congestion M. A. R. Chaudhry*, Z. Asad, A. Sprintson, and J. Hu
• 978-1-4244-6455-5/10/$26.00 2010 IEEE 38 11th Int'l Symposium on Quality Electronic Design VLSI circuits of 45nm technology and beyond are
• Buffering Interconnect: From Basics to Breakthroughs
• Navigating Registers in Placement for Clock Network Minimization
• Fast Algorithms For Slew Constrained Minimum Cost Buffering
• Library Cell Layout with Alt-PSM Compliance and Composability Ke Cao, Puneet Dhawan and Jiang Hu
• A Placement Methodology for Robust Clocking Ganesh Venkataraman, Jiang Hu
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 8, AUGUST 2008 1385 Robust Clock Tree Routing in the
• DESIGN FOR MANUFACTURABILITY ASIC design flow considering lithography-induced
• Gate Sizing For Cell Library-Based Designs Department of ECE
• Unified Adaptivity Optimization of Clock and Logic Signals
• 750 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 6, JUNE 2005 [15] S. S. Leung and M. A. Shanblatt, ASIC System Design With VHDL: A
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 5, MAY 2003 573 A Practical Methodology for Early Buffer and
• Built-In Proactive Tuning System for Circuit Aging Resilience Nimay Shah1
• SIMULTANEOUS BUFFER INSERTION AND NONHANAN OPTIMIZATION FOR VLSI INTERCONNECT UNDER A HIGHER ORDER AWE MODEL
• Performance Driven Global Routing Through Gradual Refinement \Lambda IBM Microelectronics
• Timing Driven Track Routing Considering Coupling Capacitance and Rabi Mahapatra
• Wire Sizing and Spacing for Lithographic Printability Optimization Ke Cao, Jiang Hu, Mosong Cheng
• Process Variation Aware Clock Tree Routing [Extended Abstract]
• Detecting Tangled Logic Structures in VLSI Netlists Tanuj Jindal, Charles J. Alpert, Jiang Hu, Zhuo Li, Gi-Joon Nam, Charles B. Winn
• 1614 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 12, DECEMBER 2004 A Methodology for the Simultaneous Design
• 1346 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 7, JULY 2007 Path-Based Buffer Insertion
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 11, NOVEMBER 2007 2009 Fast Algorithms for Slew-Constrained
• A Place and Route Aware Buffered Steiner Tree Construction C. N. Sze, Jiang Hu and Charles J. Alpert
• Lagrangian Relaxation for Gate Implementation Selection Yi-Le Huang
• Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems
• Transient and Fine-Grained Voltage Adaptation for Variation Resilience in VLSI Interconnects
• Gate Sizing and Device Technology Selection Algorithms for High-Performance Industrial Designs