- Maximum Instantaneous Power Estimation by Subgraph Coloring UCSD CSE Dept.
- Efficient Decoupling Capacitor Planning via Convex Programming Methods
- Reconfigurable Double Gate Carbon Nanotube Field Effect Transistor Based Nanoelectronic Architecture
- Expected Performance Centering for Analog/RF Designs Bao Liu and Andrew B. Kahng
- Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
- Signal Probability Based Statistical Timing Analysis Computer Science and Engineering Department
- SMM: Scalable Analysis of Power Delivery Networks by Stochastic Moment Andrew B. Kahng, Bao Liu and Sheldon X.-D. Tan
- SSTA-SI: Signal Integrity Effects Aware Statistical Static Timing Analysis
- Lagrangian Relaxation Based Congestion Driven Analytical Placement
- A Voltage Controlled Nano Addressing Circuit University of Texas, San Antonio TX 78249, USA,
- Statistical Gate Delay Calculation with Crosstalk Alignment Consideration
- Spatial Correlation Extraction via Random Field Simulation and Production Chip Performance Regression
- Adaptive Voltage Controlled Nanoelectronic Addressing for Yield, Accuracy and Resolution
- Advancements on Crossbar-Based Nanoscale Reconfigurable Computing Platforms
- Statistical Crosstalk Aggressor Alignment Aware Interconnect Delay Calculation
- Charge-Matching Tail Approximation in a Piece-wise Linear-and-Exponential Function University of California, San Diego
- Standard Cells StandardCells
- Minimum Decoupling Capacitor Insertion in VLSI Power/Ground Supply Networks by Semidefinite
- SSTA-SI: Statistical Static Timing Analysis in the Presence of Signal Integrity Effects
- Intel LVS Logic as a Combinational Logic Paradigm in CNT Technology
- A Linear Complexity Incremental Defect Mapping Method for Reconfigurable Computing Platforms in the Presence of Prevalent Defects
- Analysis and Extraction of Parametric Variation Effects on Microelectrofluidics-Based Biochips
- Defect Mapping and Adaptive Configuration of Nanoelectronic Circuits Based on a CNT
- Robust Differential Asynchronous Nanoelectronic Circuits Electrical and Computer Engineering Department
- Performance Variation Adaptive Differential Signaling via Carbon-Nanotube Bundles
- Analog/RF Design Techniques for High Performance Nanoelectronic On-Chip Interconnects
- Signal Probability Based Statistical Timing Analysis University of California, San Diego
- Gate Level Statistical Simulation Based on Parameterized Models for Process and Signal Variations
- Constructing Current-Based Gate Models Based on Existing Timing Library Andrew B. Kahng, Bao Liu and Xu Xu
- Supply Voltage Degradation Aware Analytical Placement Andrew B. Kahng Bao Liu Qinke Wang
- Q-Tree: A New Iterative Improvement Approach for Buffered Interconnect Optimization
- On the Skew-Bounded Minimum-Bu er Routing Tree Problem Christoph Albrecht,y
- Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control
- Interconnect Implications of Growth-Based Structural Models for VLSI Circuits Chung-Kuan Cheng1, Andrew B. Kahng1;2 and Bao Liu1
- Toward Better Wireload Models in the Presence of Obstacles Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu and Dirk Stroobandt
- Feedthrough Channel Effect on Wirelength Distribution In the Presence of Obstacles
- NP-Completeness and Approximation Scheme of Zero-Skew Clock Tree Problem
- Analytical Thermal Placement for VLSI Lifetime Improvement and Minimum Performance Variation
- Error-Detecting/Correcting-Code-Based Self-Checked/Corrected/Timed Circuits
- Statistical Gate Level Simulation via Voltage Controlled Current Source Models Bao Liu and Andrew B. Kahng
- Non-tree Routing for Reliability and Yield Improvement Andrew B. Kahng, Bao Liu, and Ion I. Mandoiu
- Stochastic Power/Ground Supply Voltage Analysis via Moment and Correlation Computation by Statistical Transient Toggling Analysis
- On VLSI Statistical Timing Analysis and Optimization
- A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew Yield
