Chang, Yao-Wen - Department of Electrical Engineering, National Taiwan University

• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 9, SEPTEMBER 2000 999 Crosstalk-Driven Interconnect Optimization by
• An ArchitectureDriven Metric for Simultaneous Placement and Global Routing for FPGAs \Lambda
• Integrating Buffer Planning with Floorplanning for Simultaneous Multi-Objective Optimization
• Rectilinear Block Placement Using B*Trees \Lambda GuangMing Wu, YunChih Chang, and YaoWen Chang
• 98 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 1, JANUARY 2009 An Integer-Linear-Programming-Based Routing
• A GraphTheoretic Sufficient Condition for FPGA/FPIC SwitchModule Routability \Lambda
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 11, NOVEMBER 2006 2513 IEEE Standard 1500 Compatible Interconnect
• YaoWen Chang ROUTING ARCHITECTURES AND ALGORITHMS
• Generic ILPbased Approaches for Dynamically Reconfigurable FPGA Partitioning GuangMing Wu 1 , JaiMing Lin 2 , Mango C.T. Chao 2 , and YaoWen Chang 3
• Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction
• 1430 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007 -Tree: A Multilevel Floorplanner for
• Spare-Cell-Aware Multilevel Analytical Placement Zhe-Wei Jiang1
• RLC COUPLING-AWARE SIMULATION FOR ON-CHIP BUSES AND THEIR ENCODING FOR DELAY REDUCTION
• 844 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 5, MAY 2008 Full-Chip Routing Considering
• 886 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 6, DECEMBER 2002 Arbitrarily Shaped Rectilinear Module Placement
• Temporal Floorplanning Using the T-tree Formulation Ping-Hung Yuh1
• Generic Universal Switch Blocks \Lambda Michael Shyu, YuDong Chang, GuangMing Wu, and YaoWen Chang
• A New Global Routing Algorithm for FPGAs \Lambda YaoWen Chang y , Shashidhar Thakur y , Kai Zhu z , and D.F. Wong y
• Design and Analysis of FPGA/FPIC Switch Modules \Lambda YaoWen Chang 1 , D. F. Wong 1 , and C. K. Wong 2y
• Novel Full-Chip Gridless Routing Considering Double-Via Insertion
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 6, JUNE 2007 1041 Multilevel Full-Chip Gridless Routing With
• Delay Modelling for Buffered RLC/RLY Trees Sheng-Lung Wang and Yao-Wen Chang
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 9, SEPTEMBER 2008 1621 MP-Trees: A Packing-Based Macro Placement
• SwitchMatrix Architecture and Routing for FPDs GuangMin Wu and YaoWen Chang
• TCG: A Transitive Closure GraphBased Representation for NonSlicing Floorplans \Lambda
• Temporal Floorplanning Using 3D-subTCG Ping-Hung Yuh1
• Arbitrary Convex and Concave Rectilinear Module Packing Using TCG Jai-Ming Lin
• 1266 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 10, OCTOBER 2001 Generic ILP-Based Approaches for Time-Multiplexed
• Generic Universal Switch Blocks Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, and Yao-Wen Chang, Member, IEEE
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 6, JUNE 2008 1055 An Optimal Network-Flow-Based Simultaneous
• FPGA Global Routing Based on a New Congestion Metric \Lambda YaoWen Chang 1 , D. F. Wong 1 , and C. K. Wong 2y
• 1928 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 BioRoute: A Network-Flow-Based Routing
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 6, JUNE 2005 869 Crosstalk-and Performance-Driven
• TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans
• CrosstalkConstrained Performance Optimization by Using Wire Sizing and Perturbation \Lambda
• B*Trees: A New Representation for NonSlicing Floorplans \Lambda YunChih Chang, YaoWen Chang, GuangMing Wu, and ShuWei Wu
• Performance-Driven Placement for Dynamically Reconfigurable FPGAs
• Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology
• TimingDriven Routing for SymmetricalArrayBased FPGAs \Lambda yz Kai Zhu 1 , YaoWen Chang 2 , and D. F. Wong 3
• Multilevel Floorplanning/Placement for Large-Scale Modules Using B*-trees
• 32 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 16, NO. 1, JANUARY 1997 Algorithms for an FPGA Switch Module Routing
• Universal SwitchModule Design for SymmetricArrayBased FPGAs \Lambda YaoWen Chang z , D. F. Wong z , and C. K. Wong xy
• NoiseConstrained Performance Optimization by Simultaneous Gate and Wire Sizing
• Joint Exploration of Architectural and Physical Design Spaces with Thermal Consideration
• Programmable Logic Devices YaoWen Chang
• A Routing Algorithm for Flip-Chip Design Jia-Wei Fang1
• Temporal Floorplanning Using the Three-Dimensional Transitive
• Placement of Digital Microfluidic Biochips Using the T-tree Formulation
• Placement with Symmetry Constraints for Analog Layout Design Using TCG-S
• Voltage Island Aware Floorplanning for Power and Timing Optimization
• Floorplan and Power/Ground Network Co-Synthesis for Fast Design Convergence
• A Clustering and Probabilitybased Approach for Timemultiplexed FPGA Partitioning \Lambda
• X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen
• Universal Switch Modules for FPGA YAO-WEN CHANG and D. F. WONG
• An Exact Jumper Insertion Algorithm for Antenna Effect Avoidance/Fixing
• Multilevel Full-Chip Routing for the X-Based Architecture Tsung-Yi Ho1
• INDUCTANCE MODELING FOR ON-CHIP INTERCONNECTS
• 654 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 4, APRIL 2008 Short Papers
• Graph MatchingBased Algorithms for FPGA Segmentation Design \Lambda y YaoWen Chang 1 , JaiMing Lin 1 , and D. F. Wong 2
• Optimal Reliable CrosstalkDriven Interconnect Optimization \Lambday Iris HuiRu Jiang 1 , SongRa Pan 2 , YaoWen Chang 2 , and JingYang Jou 1
• Quasi-Universal Switch Matrices for FPD Design
• Timing-Driven Routing for Symmetrical Array-Based FPGAs
• Analysis of FPGA/FPIC Switch Modules YAO-WEN CHANG
• Rectilinear Block Placement Using B*-Trees GUANG-MING WU
• IEEE TRANSACTIONS ON VERY LARGE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003 679 Corner Sequence--A P-Admissible Floorplan
• 28 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 1, JANUARY 2004 Timing Modeling and Optimization Under the
• 694 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 Simultaneous Floorplan and
• Reliable Crosstalk-Driven Interconnect Optimization
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 4, APRIL 2006 637 Modern Floorplanning Based on B
• 2258 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 10, OCTOBER 2006 RLC Coupling-Aware Simulation and On-Chip Bus
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007 693 Power/Ground Network and Floorplan Cosynthesis
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007 719 An Exact Jumper-Insertion Algorithm for Antenna
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 9, SEPTEMBER 2007 1625 Multilevel Full-Chip Routing With Testability
• 1818 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 10, OCTOBER 2007 An Optimal Jumper-Insertion Algorithm
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 4, APRIL 2008 643 Obstacle-Avoiding Rectilinear Steiner Tree
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 11, NOVEMBER 2008 2007 Multilayer Obstacle-Avoiding Rectilinear Steiner
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 12, DECEMBER 2008 2145 Metal-Density-Driven Placement for CMP
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 2, FEBRUARY 2009 193 A Novel Wire-Density-Driven Full-Chip Routing
• 690 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 5, MAY 2009 Voltage-Island Partitioning and Floorplanning
• 20 IEEE CIRCUITS AND SYSTEMS MAGAZINE 1531-636X/09/$26.002009 IEEE THIRD QUARTER 2009 Digital Object Identifier 10.1109/MCAS.2009.933855
• Module Placement with Boundary Constraints Using Jai-Ming Lin
• A Clustering-and Probability-based Approach for Time-multiplexed FPGA Partitioning
• Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
• INDUCTANCE MODELING FOR ON-CHIP INTERCONNECTS Shang-Wei Tu*, Wen-Zen Shen*, Yao-Wen Chang**, and Tai-Chen Chen**
• Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning Shu-Min Li
• Simultaneous Floorplanning and Buffer Block Planning Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
• Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Jai-Ming Lin
• A Fast Crosstalk-and Performance-Driven Multilevel Routing System Tsung-Yi Ho
• A REUSABLE METHODOLOGY FOR NON-SLICING FLOORPLANNING Jer-Ming Hsu, and Yao-Wen Chang
• Multilevel Full-Chip Gridless Routing Considering Optical Proximity Correction Tai-Chen Chen1
• SoC Test Scheduling Using the B*-Tree Based Floorplanning Technique * Jen-Yi Wuu1
• Modern Floorplanning Based on Fast Simulated Annealing Tung-Chieh Chen
• NTUplace: A Ratio Partitioning Based Placement Algorithm for Large-Scale Mixed-Size Designs
• Multilevel Full-Chip Routing with Testability and Yield Enhancement Katherine Shu-Min Li1
• Simultaneous Block and I/O Buffer Floorplanning for Flip-Chip Design Chih-Yang Peng1
• A Novel Framework for Multilevel Full-Chip Gridless Routing Tai-Chen Chen Yao-Wen Chang Shyh-Chang Lin
• An Optimal Jumper Insertion Algorithm for Antenna Avoidance/Fixing on General Routing Trees with Obstacles
• A High-Quality Mixed-Size Analytical Placer Considering Preplaced Blocks and Density Constraints
• An Optimal Simultaneous Diode/Jumper Insertion Algorithm for Antenna Fixing
• Challenges and Solutions in Modern VLSI (Invited Paper)
• Thermal-driven Analog Placement Considering Device Matching
• ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips
• Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
• Multi-layer Global Routing Considering Via and Wire Capacities Chin-Hsiung Hsu, Huang-Yu Chen, and Yao-Wen Chang
• Flip-Chip Routing with Unified Area-I/O Pad Assignments for Package-Board Co-Design
• IMF: Interconnect-Driven Multilevel Floorplanning for Large-Scale Building-Module Designs
• IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults
• Comments__________________________________________________________________________________________________________ Generic Universal Switch Blocks
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 8, AUGUST 2008 1363 An Efficient Graph-Based Algorithm
• 784 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 20, NO. 6, JUNE 2001 Short Papers_______________________________________________________________________________
• Current Path Analysis for Electrostatic Discharge Hung-Yi Liu
• Universal Switch Blocks for ThreeDimensional FPGA Design GuangMing Wu, Michael Shyu, and YaoWen Chang
• An Algorithm for Dynamically Reconfigurable FPGA Placement GuangMing Wu 1 , JaiMing Lin 2 , and YaoWen Chang 3
• Performance Optimization by Wire and Buffer Sizing Under the Transmission Line Model \Lambda
• 1228 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 7, JULY 2008 NTUplace3: An Analytical Placer for Large-Scale
• 286 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 2, FEBRUARY 2008 A New Multilevel Framework for Large-Scale
• Inductance Extraction for General Interconnect Structures Chun-Ying Lai1, Shyh-Kang Jeng2, Yao-Wen Chang3, and Chia-Chun Tsai4
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 5, MAY 2004 793 Short Papers_______________________________________________________________________________
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007 1417 A Network-Flow-Based RDL Routing Algorithmz
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 6, JUNE 2009 791 Analog Placement Based on
• A Novel Framework for Multilevel Routing Considering Routability and Performance
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 9, SEPTEMBER 2009 1295 A Progressive-ILP-Based Routing Algorithm for the
• Placement of Defect-Tolerant Digital Microfluidic Biochips Using the
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, VOL. XX, NO. Y, MONTH 2003 1 TCG: A Transitive Closure Graph-Based
• Fast PerformanceDriven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation \Lambda
• 968 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 6, JUNE 2004 TCG-S: Orthogonal Coupling of -Admissible