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Tasiran, Serdar - Department of Computer Engineering, Koc University
A Functional Validation Technique: Biased-Random Simulation Guided by Observability-Based Coverage
Using a Formal Specification and a Model Checker to Monitor and Direct Simulation
BDD Variable Ordering for Interacting Finite State Machines
Goldilocks: Efficiently Computing the Happens-Before Relation Using Locksets
CORRECTING FUNCTIONAL ERRORS in hard-ware designs can be very costly, thus placing
TreeJuxtaposer: Scalable Tree Comparison using Focus+Context with Guaranteed Visibility
A CausalityA Causality--Based RuntimeBased Runtime Check for (Rollback) AtomicityCheck for (Rollback) Atomicity
(A Work-in-progress Paper) A Novel Test Coverage Metric for
Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in Multi-Core Systems
Runtime Refinement Checking of Concurrent Data Structures
Rollback Atomicity Serdar Tasiran and Tayfun Elmas
Synergies for Design Verification 472 0740-7475/04/$20.00 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
Using Formal Specifications to Monitor and Guide Simulation: Verifying the Cache Coherence Engine of the Alpha 21364 Microprocessor
Compositional and Hierarchical Techniques for the Formal Veri cation of Real-Time Systems
Microsoft Research PhD Scholarship Software Verification and Reliability for Multi-Core Processors
Simplifying Linearizability Proofs with Reduction and Abstraction
Simplifying Linearizability Proofs with Reduction and Abstraction
An Annotation Assistant for Interactive Debugging of Programs with Common Synchronization Idioms
A Calculus of Atomic Actions Tayfun Elmas
Stochastic Modeling and Optimization for Energy Management in Multi-Core Systems
Stochastic Logical Effort: Designing for Timing Yield on the Back of an Envelope
Promising Directions in Hardware Design Verification Shaz Qadeer Serdar Tasiran
An Assume-Guarantee Rule for Checking Simulation
Computing Delay with Coupling Using Timed Automata Serdar Tasiran
On Iterative Veri cation with Timed Automata Serdar Tas ran Robert K. Brayton
This article was processed using the LATEX macro package with LLNCS style Appendix: Proofs
HSIS: A BDD-Based Environment for Formal Verification A. Aziz, F. Balarin, S. T. Cheng, R. Hojati, T. Kam, S. C. Krishnan, R. K. Ranjan,
Goldilocks: AGoldilocks: A RaceRace andand TransactionTransaction--AAware Java Runtimeware Java Runtime
Coverage-Directed Generation of Biased Random Inputs for Functional Validation of Sequential Circuits
VyrdMC: Driving Runtime Refinement Checking with Model Checkers
Smart Monte Carlo for Yield Estimation Serdar Tasiran Alper Demir
Goldilocks: A Race and Transaction-Aware Java Runtime Tayfun Elmas
Precise Race Detection and Efficient Model Checking Using Locksets
VYRD: VerifYing Concurrent Programs by Runtime Refinement-Violation Detection