Mishra, Prabhat - Department of Computer and Information Science and Engineering, University of Florida

• Generating Test Programs to Cover Pipeline Interactions Thanh Nga Dang Abhik Roychoudhury Tulika Mitra Prabhat Mishra
• A Retargetable Software Timing Analyzer Using Architecture Description Language
• Shrinking time to market, coupled with short product lifetimes, has created
• A Framework for Fast, Flexible and Retargetable Instruction-Set Architecture Simulation
• A Distributed Approach to Maintain Network Connectivity in Mobile Ad-Hoc Networks Samir Biswas 1
• Instruction Set CompiledSimulation: A Technique for Fast and FlexibleInstruction Set Simulation
• Modeling and Validation of Pipeline Specifications
• Language-driven Validation of Pipelined Processors using Satisfiability Solvers
• A Novel Test-Data Compression Technique using Application-Aware Bitmask and Dictionary Selection
• Memory Subsystem Description in EXPRESSION Prabhat Mishra Peter Grun Nikil Dutt Alex Nicolau
• Temperature-aware Task Partitioning for Real-Time Scheduling in Embedded Systems
• Bitmask-based Control Word Compression for NISC Architectures Chetan Murthy and Prabhat Mishra
• Power-Adaptive Routing Topology for Remote Sensor Networks
• Efficient Trace Data Compression using Statically Selected Dictionary Kanad Basu and Prabhat Mishra
• Efficient Trace Signal Selection for Post Silicon Validation and Debug Kanad Basu and Prabhat Mishra
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 4, APRIL 2008 673 Bitmask-Based Code Compression
• Lossless Compression using Efficient Encoding of Bitmasks Chetan Murthy and Prabhat Mishra
• Efficient Combination of Trace and Scan Signals for Post Silicon Validation and Debug
• Proceedings of the International Conference on Resource Utilisation and Intelligent Systems,
• Dual Code Compression for Embedded Systems Kartik Shrivastava and Prabhat Mishra
• Architecture description languages for programmable embedded systems
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 9, SEPTEMBER 2010 1277 Test Data Compression Using Efficient Bitmask and
• Processor-MemoryCo-Exploration driven by a Memory-Aware Architecture DescriptionLanguage!*
• Rapid Exploration of Pipelined Processors through Automatic Generation of Synthesizable RTL Models
• MRI-image based radiotherapy treatment optimization of brain tumours using stochastic approach
• Functional Validation of Programmable Architectures Prabhat Mishra Nikil Dutt
• Specification-based Compaction of Directed Tests for Functional Validation of Pipelined Processors
• Test Generation using SAT-based Bounded Model Checking for Validation of Pipelined Processors
• MEMSNANO-2005 International conference on MEMS and Semiconductor Nanotechnology
• Synchronized Generation of Directed Tests using Satisfiability Solving Xiaoke Qin, Mingsong Chen and Prabhat Mishra
• A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. XX, NO. NN, MMM YYYY 1 System-Wide Leakage-Aware Energy Minimization
• A Novel Distributed Algorithm to Maintain Connectivity with Fault Tolerance Scheme in Mobile Ad-Hoc
• Dynamic Cache Reconfiguration for Soft Real-Time Systems WEIXUN WANG, University of Florida
• SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems
• Leakage-Aware Energy Minimization using Dynamic Voltage Scaling and Cache
• DESIGNING A REAL TIME SYSTEM FOR CAR NUMBER DETECTION USING DISCRETE HOPFIELD NETWORK
• Hybrid Compiled Simulation: An Efficient Technique for Instruction-Set Architecture Simulation1
• Memory Access Optimizations in Instruction-Set Simulators Mehrdad Reshadi
• Dynamic Reconfiguration of Two-Level Caches in Soft Real-Time Embedded Systems
• A Brief History of Multiprocessors and EDA Sandeep Shukla
• AutomaticFunctional Test ProgramGeneration for Pipelined Processors using Model Checking
• A Bitmask-based Code Compression Technique for Embedded Systems
• Towards RTL Test Generation from SystemC TLM Specifications Mingsong Chen Prabhat Mishra Dhrubajyoti Kalita
• Coprocessor Codesign for Programmable Architectures Prabhat Mishra Frederic Rousseau Nikil Dutt Alex Nicolau
• An Efficient Retargetable Framework for Instruction-Set Simulation Mehrdad Reshadi, Nikhil Bansal, Prabhat Mishra, Nikil Dutt
• Functional Verification and Testbench Generation 122 0740-7475/04/$20.00 2004 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers
• Automatic Verification of In-Order Execution in Microprocessors with Fragmented Pipelines and Multicycle Functional Units
• Efficient Decision Ordering Techniques for SAT-based Test Generation Mingsong Chen Xiaoke Qin Prabhat Mishra
• Peer-to-Peer Assisted Voice Communication using Cell Phones CISE Technical Report 05-005
• Functional Verification of Pipelined Processors: A Case Study Prabhat Mishra Nikil Dutt Yaron Kashai
• Int J Parallel Prog (2009) 37:343344 DOI 10.1007/s10766-009-0112-y
• Guest Editorial Prabhat Mishra
• Architecture Description Language driven Verification of In-Order Execution in Pipelined Processors
• Processor-Memory Coexploration Using an Architecture Description Language
• Temperature-and Energy-Constrained Scheduling in Multitasking Systems: A Model Checking Approach
• 1224 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 28, NO. 8, AUGUST 2009 A Universal Placement Technique of Compressed
• Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study
• Coverage-driven Automatic Test Generation for UML Activity Diagrams Mingsong Chen, Prabhat Mishra
• Coverage-driven Functional Test Generation for Processor Validation using Formal Methods
• Automatic Validation of Pipeline Specifications Prabhat Mishra Nikil Dutt Alex Nicolau
• Functional Test Generation using SAT-based Bounded Model Checking
• Graph-based Functional Test Program Generation for Pipelined Processors Prabhat Mishra Nikil Dutt
• FunctionalAbstractiondriven DesignSpace Exploration of HeterogeneousProgrammableArchitectures
• Efficient Techniques for Directed Test Generation using Incremental Satisfiability Prabhat Mishra and Mingsong Chen
• Property Learning Techniques for Efficient Generation of Directed Tests
• Design Automation for Embedded Systems, 8, 249265, 2003. # 2003 Kluwer Academic Publishers, Boston. Manufactured in The Netherlands.
• Specification-driven Directed Test Generation for Validation of Pipelined Processors
• Challenges of Rapidly Emerging Consumer Space Multiprocessors
• Des Autom Embed Syst (2010) 14: 105130 DOI 10.1007/s10617-010-9052-4
• Efficient Placement of Compressed Code for Parallel Decompression Xiaoke Qin and Prabhat Mishra
• A Study of Out-of-Order Completion for the MIPS R10K Superscalar Processor
• Synergistic Integration of Dynamic Cache Reconfiguration and Code Compression in Embedded Systems*
• 14 Int. J. Embedded Systems, Vol. 1, Nos. 1/2, 2005 Copyright 2005 Inderscience Enterprises Ltd.
• Specification of Hazards, Stalls, Interrupts, and Exceptions in Prabhat Mishra Nikil Dutt Alex Nicolau
• Synthesis-driven Exploration of Pipelined Embedded Processors Prabhat Mishra Arun Kejariwal Nikil Dutt
• Architecture Description Language Driven Design Space Exploration in the Presence of Coprocessors
• A Retargetable Framework for Instruction-Set Architecture Simulation
• Automated Micro-architectural Test Generation for Validation of Modern Processors
• Efficient Directed Test Generation for Validation of Multicore Architectures Xiaoke Qin and Prabhat Mishra
• A Property Checking Approach to Microprocessor Verification using Symbolic Simulation
• Dynamic Reconfiguration of Two-Level Cache Hierarchy in Real-Time Embedded Systems*
• UNIVERSITY OF CALIFORNIA, Specification-driven Validation of
• PreDVS: Preemptive Dynamic Voltage Scaling for Real-time Systems using Approximation Scheme
• Automatic RTL Test Generation from SystemC TLM Specifications
• Decoding-aware Compression of FPGA Bitstreams Xiaoke Qin, Student Member, Chetan Muthry, and Prabhat Mishra, Senior Member, IEEE
• Dynamic Cache Reconfiguration and Partitioning for Energy Optimization in Real-Time Multicore Systems
• Lossless Audio Compression: A Case Study CISE Technical Report 08-415
• Architecture Description Language (ADL)-Driven Software Toolkit Generation
• A Partitioned Bitmask-based Technique for Lossless Seismic Data Compression
• Functional Abstraction of Programmable Embedded Systems Prabhat Mishra Jonas Astrom Nikil Dutt Alex Nicolau
• Architecture Description Language driven Validation of Processor, Memory, and Co-Processor Pipelines
• Reliability Improvement in Multicore Architectures Through Computing in Embedded Memory
• Prediction of EEG Signal by Digital Filtering Ayan Banerjee1
• Decision Ordering Based Property Decomposition for Functional Test Generation Mingsong Chen Prabhat Mishra
• 396 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 3, MARCH 2010 Functional Test Generation Using Efficient Property
• DICTIONARY-BASED CODE COMPRESSION TECHNIQUES USING BIT-MASKS FOR EMBEDDED SYSTEMS
• Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language
• COVERAGE-DRIVEN TEST GENERATION FOR FUNCTIONAL VALIDATION OF PIPELINED PROCESSORS
• A Novel Distributed Algorithm for Topology Management in Mobile Ad-hoc Networks
• An Efficient Code Compression Technique using Application-Aware Bitmask and Dictionary Selection Methods
• DECODING-AWARE COMPRESSION TECHNIQUES FOR RECONFIGURABLE CHETAN MURTHY
• Guest Editors' Introduction: Multicore SoC Validation with
• Architecture Description Language driven Functional Test Program Generation for Microprocessors using SMV
• Sustainable Computing: Informatics and Systems 1 (2011) 3545 Contents lists available at ScienceDirect
• SAT-based Combinational Equivalence Checking Zhuo Huang Prabhat Mishra
• Functional Test Generation using Property Decompositions for Validation of Pipelined Processors
• HDLGen: Architecture Description Language driven HDL Generation for Pipelined Processors
• Functional Test Generation Using Design and Property Decomposition Techniques
• A Methodology for Validation of Microprocessors using Equivalence Checking
• Synergistic Integration of Code Encryption and Compression in Embedded Systems
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. NN, MMM YYYY 1 TCEC: Temperature-and Energy-Constrained
• Memory-based Computing for Performance and Energy Improvement in Multicore Architectures