- Compositionally Progressive Solutions of Synchronous Language Nina Yevtushenko
- Higher-Order Flexibilities in Multi-Valued Networks Alan Mishchenko Robert K. Brayton
- Fishbone: A Block-Level Placement and Routing Scheme Fan Mo Robert K. Brayton
- HW/SW Partitioning and Code Generation of Embedded Control Applications on a Reconfigurable Architecture
- SAT-Based Complete Don't-Care Computation for Network Optimization Alan Mishchenko and Robert K. Brayton
- Improvements to Combinational Equivalence Checking Alan Mishchenko Satrajit Chatterjee Robert Brayton
- Verification after Synthesis Alan Mishchenko Robert Brayton
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 6, JUNE 2003 723 Special Section Short Papers________________________________________________
- Fast Minimum-Register Retiming via Binary Maximum-Flow Alan Mishchenko Aaron Hurst Robert Brayton
- Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton
- Automating Logic Rectification by Approximate SPFDs Yu-Shen Yang
- Functional Dependency for Verification Reduction
- EECS 219B { Midterm #2 Prof. Robert Brayton
- Composition Operators in Language Equations Nina Yevtushenko
- Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Robert Brayton
- Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations
- SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Stephen Jang
- Inductively Finding a Reachable State Space Over-Approximation
- Cutless FPGA Mapping Alan Mishchenko Sungmin Cho Satrajit Chatterjee Robert Brayton
- Benchmarking Method and Designs Targeting Logic Synthesis for FPGAs Joachim Pistorius, Mike Hutton
- Valid Clock Frequencies and Their Computation in Wavepipelined Circuits \Lambda
- SUBMITTED TO IEEE TRANSATIONS ON CAD/ICAS, NOVEMBER 13, 1992 1 Combinational Test Generation Using Satisfiability
- A Timing-Driven Module-Based Chip Design Flow University of California, Berkeley
- Comparing Two Rewiring Models March 15, 2004
- Regular Fabrics In Deep Sub-Micron Integrated-Circuit Design Fan Mo and Robert K. Brayton
- 686 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 22, NO. 6, JUNE 2003 On the Verification of Sequential Equivalence
- Scalable Logic Synthesis using a Simple Circuit Structure Alan Mishchenko Robert Brayton
- Whirlpool PLAs: A Regular Logic Structure and Their Synthesis Fan Mo and Robert K. Brayton
- Simplification of Non-Deterministic Multi-Valued Networks Alan Mishchenko Robert Brayton
- Clockless Implementation Structure and Methodology for DSM Implementation
- Integrating Logic Synthesis, Technology Mapping, and Retiming Alan Mishchenko Satrajit Chatterjee Jie-Hong Jiang Robert Brayton
- Scalable and Scalably-Verifiable Sequential Synthesis Alan Mishchenko Michael Case Robert Brayton Stephen Jang
- Recording Synthesis History for Sequential Verification Alan Mishchenko Robert Brayton
- A Simultaneous Bus Orientation and Bused Pin Flipping Algorithm
- Semi-Detailed Bus Routing with Variation Reduction 600 W California Ave
- On Resolution Proofs for Combinational Equivalence Satrajit Chatterjee Alan Mishchenko
- Sequential Rewriting and Synthesis Robert Brayton Alan Mishchenko
- Fast Boolean Matching for LUT Structures Alan Mishchenko Satrajit Chatterjee Robert Brayton
- Scalably-Verifiable Sequential Synthesis Robert Brayton Alan Mishchenko
- Scalable Sequential Verification Robert Brayton Alan Mishchenko
- Symmetry Detection for Large Boolean Functions using Circuit Representation, Simulation and Satisfiability
- DAG-Aware AIG Rewriting A Fresh Look at Combinational Logic Synthesis
- The Advantages of Latch-Based Design Under Process Aaron P. Hurst, Robert K. Brayton
- Improvements to Technology Mapping for LUT-Based FPGAs Alan Mishchenko Satrajit Chatterjee Robert Brayton
- Sequential Synthesis with Co-Bchi Specifications Guoqiang Wang, Alan Mishchenko,
- Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton
- A Theory of Non-Deterministic Networks Alan Mishchenko and Robert Brayton
- Synthesis Methodology for Built-In At-Speed Testing Yinghua Li, Alex Kondratyev*, and Robert Brayton
- An Integrated Technology Mapping Environment Alan Mishchenko Satrajit Chatterjee Robert Brayton Maciej Ciesielski
- Efficient Solution of Language Equations Using Partitioned Representations Alan Mishchenko, Robert Brayton, Roland Jiang
- FRAIGs: A Unifying Representation for Logic Synthesis and Verification Alan Mishchenko, Satrajit Chatterjee, Roland Jiang, Robert Brayton
- An Integrated Standard-Cell Physical Design Algorithm Abstract --An integrated standard-cell physical design algorithm
- A Theory of Non-Deterministic Networks Alan Mishchenko and Robert K. Brayton
- Generalized Cofactoringfor Logic Function Evaluation Yunjian Jiang Slobodan Matic Robert K. Brayton
- Checkerboard: A Regular Structure and its Synthesis Fan Mo and Robert K. Brayton
- Don't Cares in Logic Minimization of Extended Finite State Machines Yunjian Jiang Robert K. Brayton
- Software Synthesis from Synchronous Specifications Using Logic Simulation Techniques
- Optimization of Multi-Valued Multi-Level Networks M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko*, S. Sinha, T. Villa**, and R. Brayton
- Using Problem Symmetry in Search Based Satisfiability Algorithms Evgueni I. Goldberg
- Combinational and Sequential Mapping with Priority Cuts Alan Mishchenko Sungmin Cho Satrajit Chatterjee Robert Brayton
- Efficient FPGA Mapping using Priority Cuts Sungmin Cho Satrajit Chatterjee Alan Mishchenko Robert Brayton
- SAT-Based Logic Optimization and Resynthesis Alan Mishchenko Robert Brayton Jie-Hong Roland Jiang Stephen Jang
- Factor Cuts Satrajit Chatterjee Alan Mishchenko Robert Brayton
- IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 5, MAY 2006 743 Using Simulation and Satisfiability to Compute
- On Breakable Cyclic Definitions Jie-Hong R. Jiang, Alan Mishchenko, and Robert K. Brayton
- A Boolean Paradigm in Multi-Valued Logic Synthesis Alan Mishchenko Robert K. Brayton
- Abstract--We present a formulation of retiming to minimize the number of registers in a design by iterating a maximum
- 1020 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 7, JULY 2004 SPFD-Based Wire Removal in Standard-Cell and
- SAT-Based Complete Don't-Care Computation for Network Optimization Alan Mishchenko Robert K. Brayton
- 2674 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 12, DECEMBER 2006 Retiming and Resynthesis: A Complexity Perspective
- Equivalences for fair Kripke structures Adnan Aziz Vigyan Singhal Felice Balarin
- Sequential Optimization in the Absence of Global Reset
- Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton
- Reducing Structural Bias in Technology Mapping S. Chatterjee A. Mishchenko R. Brayton
- River PLAs: A Regular Circuit Structure Fan Mo and Robert K. Brayton
- Topologically Constrained Logic Synthesis Subarnarekha Sinha
- Multi{Valued Optimization on Post Logic Networks April 16, 2002
- Synthesis Methodology for Built-In At-Speed Testing Yinghua Li, Alex Kondratyev*, and Robert Brayton
- EECS 219B { Midterm #1 Prof. Robert Brayton
- Sequential Synthesis by Language Equation Solving Nina Yevtushenko
- A Theory of Non-Deterministic Networks Alan Mishchenko and Robert Brayton
- Automated Extraction of Inductive Invariants to Aid Model Checking
- Minimizing Implementation Costs with End-to-End Aaron P. Hurst Alan Mishchenko Robert Brayton
- Exploring Multi-Valued Minimization Using Binary Methods Alan Mishchenko
- Computing Clock Skew Schedules Under Normal Process Variation
- Gaining Predictability and Noise Immunity in Global Interconnects UC Berkeley
- Observability Relations for MultiOutput Nodes \Lambda Hamid Savoj Robert K. Brayton
- Whirlpool PLAs: A Regular Logic Structure and Their Synthesis Fan Mo and Robert K. Brayton
- A Linear Time Algorithm for Optimum Tree Placement Satrajit Chatterjee Zile Wei Alan Mishchenko Robert Brayton
