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Niu, Guofu - Department of Electrical and Computer Engineering, Auburn University
Expt. 10 T. Roppel Oct. 15, 2009 ELEC 2210 EXPERIMENT 10
Rev. 8/26/ 2009 ELEC 2210 -EXPERIMENT 3
T. Roppel Oct. 2009 ELEC 2210 EXPERIMENT 9
Updated 3/7/2011 ELEC 2210 EXPERIMENT 8
Zener Diodes and LED's Rev. 6/11/09 ELEC 2020 EXPERIMENT 6
N-CHANNEL ENHANCEMENT MODE VERTICAL DMOS FET
Symbol Max p-channel Units TJ, TSTG C
2001 Fairchild Semiconductor Corporation DS009796 www.fairchildsemi.com October 1988
ELEC 2210 Experiment 2 (Rev. 8/19/2009) EXPERIMENT 2
Revised 8/26/2009 EXPERIMENT 4
Exp. 7 BJT Rev. 9/23/09 ELEC 2210 EXPERIMENT 7
T. Roppel Nov. 2009 ELEC 2210 EXPERIMENT 12
2210 Experiment 13 CMOS Logic T. Roppel Nov. 2009 1
DM54LS154DM74LS1544-Lineto16-LineDecodersDemultiplexers DM54LS154 DM74LS154 4-Line to 16-Line
REV 8/18/09 Roppel 1 ELEC 2210 -EXPERIMENT 1
54LS151DM54LS151DM74LS151DataSelectorMultiplexer 54LS151 DM54LS151 DM74LS151
Prices effective Fall 2007 Subject to sales taxes.
Revised 01/19/2010 EXPERIMENT 5
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 5, MAY 1999 1007 Measurement of Collector-Base Junction
10-MINUTE TUTORIAL DIGITAL LOGIC CIRCUIT MODELING AND SIMULATION WITH MULTISIM
ELEC 2210 Experiment 2 (Rev. 5/19/2011) EXPERIMENT 2
Rev. 8/26/ 2009 ELEC 2210 -EXPERIMENT 3
Revised 5/27/2011 EXPERIMENT 4
Common Cathode Page 1 of 10
2007 Fairchild Semiconductor Corporation 1 www.fairchildsemi.com 1N4728A -1N4758A Rev. H1
0 0.2 0.4 0.6 0.8 1 eDe(/Silicon/R1_n5_000003_des.dat)
INSIDE FRONT COVER Section 1 Specification
S a m u e l G i n n College of Engineering
