- Exploiting Streams in Instruction and Data Address Trace Compression Aleksandar Milenkovi , Milena Milenkovi
- 0-7803-8808-9/05/$20.00 2005 IEEE An Environment for Runtime Power Monitoring
- Hardware Support for Code Integrity in Embedded Processors
- Using Instruction Block Signatures to Counter Code Injection Attacks Milena Milenkovic, Aleksandar Milenkovic, Emil Jovanov
- Journal of Mobile Multimedia, Vol. 1, No.4 (2006) 307-326 Rinton Press
- Huntsville Chapter of the IEEE Computer Society (http://ewh.ieee.org/r3/huntsville/cs/), Department of Electrical and Computer Engineering (http://www.ece.uah.edu/), LaCASA Laboratory
- Security Extensions for Integrity and Confidentiality in Embedded Processors
- An Efficient Single-Pass Trace Compression Technique Utilizing Instruction Streams
- Manuscript received December 15, 2004. A. Milenkovic is with the Electrical and Computer Engineering
- Using Instruction Block Signatures to Counter Code Injection Attacks Milena Milenkovi, Aleksandar Milenkovi, Emil Jovanov
- Abstract--Trace-driven simulation has long been used in both processor and memory studies. The large size of traces motivated
- 36 1092-3063/00/$10.00 2000 IEEE IEEE Concurrency Achieving High
- A major problem in teaching com-puter architecture and organization courses is
- MicroelectronicsJournal27 (1996) 11-22 Copyright ~) 1996 Elsevier Science Limited
- A Low Overhead Hardware Technique for Software Integrity and Confidentiality
- Abstract--Design of low-cost, miniature, lightweight, ultra low-power, intelligent sensors capable of
- Execution Characteristics of SPEC CPU2000 Benchmarks: Intel C++ vs. Microsoft VC++
- Performance Evaluation of Cache Replacement Policies for the SPEC CPU2000 Benchmark Suite
- N-TUPLE COMPRESSION: A NOVEL METHOD FOR COMPRESSION OF BRANCH INSTRUCTION TRACES
- Teaching IP Core Development: An Example Aleksandar Milenkovic, David Fatzer
- Demystifying Intel Branch Predictors Milena Milenkovic, Aleksandar Milenkovic, Jeffrey Kulick
- Cache Injection on Bus Based Multiprocessors Aleksandar Milenkovic, Veljko Milutinovic
- A Hierarchical Memory System Environment J. Djordjevic, A. Milenkovic, S.Prodanovic*
- An Educational Environment for Teaching a Course in Computer Architecture and Organization
- Lazy Prefetching Aleksandar Milenkovic, Veljko Milutinovic
- ARCHITECTURES FOR RUN-TIME VERIFICATION OF CODE INTEGRITY
- Huntsville Chapter of the IEEE Computer Society (http://ewh.ieee.org/r3/huntsville/cs/), Department of Electrical and Computer Engineering (http://www.ece.uah.edu/), LaCASA Laboratory
- Experiment Flows and Microbenchmarks for Reverse Engineering of Branch Predictor Structures
- CALKAS: A Computer Architecture Learning and Knowledge Assessment System
- : Computer Aided Learning in Computer
- Exploiting Streams in Instruction and Data Address Trace Compression Aleksandar Milenkovi#, Milena Milenkovi#
- A Performance Evaluation of Memory Hierarchy in Embedded Systems Aleksandar Milenkovic, Milena Milenkovic, Nelson Barnes
- An Integrated Educational Environment for Computer Architecture and Organisation
- BioMed Central Page 1 of 10
- An Integrated Educational Environment for Teaching Computer Architecture and Organisation
- Abstract--Recent advances in sensors, low-power system-on-a-chip devices, and wireless communications, have prompted a
- A Real-Time Program Trace Compressor Utilizing Double Move-to-Front Method
- SOFTWARE--PRACTICE AND EXPERIENCE Softw. Pract. Exper. 2004; (in press) (DOI: 10.1002/spe.572)
- Microbenchmarks For Determining Branch Predictor Organization Milena Milenkovic, Aleksandar Milenkovic, Jeffrey Kulick
- Using Instruction Block Signatures to Counter Code Injection Attacks Milena Milenkovi#, Aleksandar Milenkovi#, Emil Jovanov
- An Approach to Characterization of Parallel Applications for DSM Systems 'DUNR 0DULQRY 'DYRU 0DJGL $OHNVDQGDU 0LOHQNRYL
- 0-7803-8808-9/05/$20.00 2005 IEEE Time Synchronization for ZigBee Networks
- 264 IEEE TRANSACTIONS ON EDUCATION, VOL. 48, NO. 2, MAY 2005 Flexible Web-Based Educational System for Teaching
- LOOKUP TABLE BASED REAL-TIME NON-UNIFORMITY CORRECTION OF INFRARED SCENE PROJECTORS
- A performance evaluation of cache injection in bus-based shared memory multiprocessors
- A Framework For Trusted Instruction Execution Via Basic Block Signature Verification
- An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors
- A Performance Evaluation of Cache Injection in Busbased Shared Memory Multiprocessors
- Abstract---Tracedriven simulation has long been used in both processor and memory studies. The large size of traces motivated
- Abstract--This paper describes a prototype system for continual health monitoring at home. The system consists of an
- Wireless sensor networks for personal health monitoring: Issues and an implementation
