Chan Carusone, Tony - Department of Electrical and Computer Engineering, University of Toronto

• A 15-Gb/s Preamplifier with 10-dB Gain Control and 8-mV Sensitivity in 65-nm CMOS
• 2224 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 10, OCTOBER 2006 A 1-Tap 40-Gb/s Look-Ahead Decision Feedback
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 53, NO. 9, SEPTEMBER 2006 807 An Equalizer Adaptation Algorithm to
• A 1-Tap 40-Gbps Look-ahead Decision Feedback Equalizer in 0.18m SiGe BiCMOS Technology
• A 5-Gbps Optical Receiver with Monolithically Integrated Photodetector in 0.18-m CMOS
• DIGITAL ALGORITHMS FOR ANALOG ADAPTIVE FILTERS
• 2138 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 8, AUGUST 2009 CMOS Oscillators for Clock Distribution and
• Electronic Dispersion Compensation of 40-Gb/s Multimode Fiber Links Using IIR Equalization
• Progress and Trends in Multi-Gbps Optical Receivers with CMOS Integrated Photodetectors
• 1772 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 8, AUGUST 2008 A Delta-Sigma Modulator With a Widely
• A 30-GS/sec Track and Hold Amplifier in 0.13-m CMOS Technology
• 858 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 55, NO. 9, SEPTEMBER 2008 A Time-Interleaved 16-DAC Architecture Clocked
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 4, APRIL 2006 909 A CMOS Finite Impulse Response Filter
• The Effect of Redundancy on Mismatch-Induced Offset and Random Noise in a Dynamic Comparator
• A Flexible Hardware Encoder for Systematic Low-Density Parity-Check Codes
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 6, JUNE 2011 1337 7.4 Gb/s 6.8 mW Source Synchronous Receiver
• 158 2010 IEEE International Solid-State Circuits Conference ISSCC 2010 / SESSION 8 / HIGH-SPEED WIRELINE TRANSCEIVERS / 8.2
• Analog adaptive filters with digitally programmable coefficients can provide speed, power, and area
• A D-Band PLL Covering the 81-82 GHz, 86-92 GHz and 162-164 GHz Bands
• A 20-Gb/s Coaxial Cable Receiver Analog Front-End in 90-nm CMOS Technology
• A 5TH ORDER GM-C FILTER IN 0.25M CMOS WITH DIGITALLY PROGRAMMABLE POLES & ZEROES Anthony Chan Carusone and David A. Johns
• A Comparison of Equalizers for Compensating Polarization-Mode Dispersion
• Two-tap travelling-wave infinite impulse response filter with 12 dB peaking at 24 GHz
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 9, SEPTEMBER 2003 539 Digital LMS Adaptation of Analog Filters Without
• IEEE International Sytnposium onCircuit and System2003 TutorialGuide 4. Analog Adaptive Filters
• Abstract ? By splitting the input sampling capacitor of a modulator into several time-interleaved branches, FIR filtering
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 54, NO. 10, OCTOBER 2007 2137 Modeling and Design of Multilevel BangBang
• CLOCK RECOVERY IN HIGH-SPEED MULTILEVEL SERIAL LINKS Faisal A. Musa and Anthony Chan Carusone
• ANALOG FILTER ADAPTATION USING A DITHERED LINEAR SEARCH ALGORITHM Anthony Chan Carusone and David A. Johns
• 74 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 55, NO. 1, JANUARY 2008 Block-Interlaced LDPC Decoders With Reduced
• SiGe BiCMOS for Analog, High-Speed Digital and Millimetre-Wave Applications Beyond 50 GHz
• Abstract--This paper presents a 40-GSamples/sec Track & Hold Amplifier (THA). The chip is manufactured in
• This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. SUBMITTED: IEEE TRANSACTION ON CIRCUITS AND SYSTEMS-I, VOL. , NO. , SEPTEMBER 2008 1
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 5, MAY 2011 1011 Design of a Dual W-and D-Band PLL
• 2844 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS A 5-Gbit/s CMOS Optical Receiver With Integrated
• 1794 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 56, NO. 8, AUGUST 2009 A 32/16-Gb/s Dual-Mode Pulsewidth Modulation
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 6, JUNE 2009 1709 A 35-GS/s, 4-Bit Flash ADC With Active Data
• 298 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 32, NO. 2, MAY 2009 Frequency-Division Bidirectional Communication
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 8, AUGUST 2008 1835 Power Reduction Techniques for LDPC Decoders
• 56 IEEE CIRCUITS AND SYSTEMS MAGAZINE SECOND QUARTER 2008 by Anthony Chan Carusone
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 53, NO. 12, DECEMBER 2006 1393 A Baud-Rate Timing Recovery Scheme With a
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 1919 A 3-Tap FIR Filter With Cascaded Distributed
• 294 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 48, NO. 3, MARCH 2001 Differential Signaling with a Reduced Number
• A 32/16 Gb/s 4/2-PAM Transmitter with PWM Pre-Emphasis and 1.2 Vpp per side Output Swing in
• A 38-Gb/s 2-tap Transversal Equalizer in 0.13-m CMOS using a Microstrip Delay Element
• A Delta-Sigma Modulator with a Widely Programmable Center Frequency and
• Practical Challenges for Electronic Dispersion Compensation in CMOS
• A 14-Gb/s 32 mW AC coupled receiver in 90-nm CMOS Masum Hossain, Anthony Chan Carusone
• Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip Links
• A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18-m CMOS
• A Bit-Serial Approximate Min-Sum LDPC Decoder and FPGA Implementation
• A 40 Gb/s Transversal Filter in 0.18 m CMOS Using Distributed Amplifiers
• A 3-Tap Digitally Programmable Transversal Filter in 90 nm CMOS for Equalization up to 30 Gb/s
• Jitter Equalization for Binary Baseband Communication
• Multi-Gbit/sec Low Density Parity Check Decoders with Reduced Interconnect Complexity
• A SIGMA-DELTA BASED OPEN-LOOP FREQUENCY MODULATOR Denis Daly and Anthony Chan Carusone
• AA SSIIGGMMAA--DDEELLTTAA BBAASSEEDD OOPPEENN--LLOOOOPP FFRREEQQUUEENNCCYY MMOODDUULLAATTOORR
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 10, OCTOBER 2006 2233 Design Methodology for a 40-GSamples/s
• A 6.5 Gb/s Backplane Transmitter with 6-tap FIR Equalizer and Variable Tap Spacing
• 524 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 3, MARCH 2010 510 Gb/s 70 mW Burst Mode AC Coupled Receiver
• An 81Gb/s, 1.2V TIALA-Retimer in Standard 65nm CMOS Shahriar Shahramian1
• 20 GHz Low Power QVCO and De-skew Techniques in 0.13m Digital CMOS
• Gain and Equalization Adaptation to Optimize the Vertical Eye Opening in a Wireline Receiver
• A 3.3-Gbps Bit-Serial Block-Interlaced Min-Sum LDPC Decoder in 0.13-m CMOS
• HARDWARE REDUCTION BY COMBINING PIPELINED A/D CONVERSION AND FIR FILTERING FOR CHANNEL EQUALIZATION
• 1832 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 46, NO. 8, AUGUST 2011 CMOS Technology Scaling Considerations for
• A 1-1-1-1 MASH Delta-Sigma Modulator Using Dynamic Comparator-Based OTAs