- COMPARATIVE ANALYSIS OF SERIAL VS PARALLEL LINKS IN NOC Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar
- Trace Cache Sampling Filter Michael Behar
- 2005 SRC Review Power and Area EfficientPower and Area Efficient
- IngeniareIngeniare (Latin)(Latin) EngineerEngineer IngenuityIngenuity
- The Innovation Paradox: Reconciling Creativity & Discipline How Winning Organizations Combine Inspiration With Perspiration
- Fast Asynchronous Shift Register for Bit-Serial Communication Rostislav (Reuven) Dobkin, Ran Ginosar, Avinoam Kolodny
- Shmuel Wimer 1,2 , Konstantin Moiseev2
- Best of Both Worlds: A Bus Enhanced NoC (BENoC) Ran Manevich1
- CORRESPONDENCE smaller by a factorof two, the error would be about20 percent.
- Trace classification and its use for profile-based trace cache management
- BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
- An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design
- Abstract--The Unified Logical Effort (ULE) model for delay evaluation and minimization in paths composed of CMOS logic
- Access Regulation to Hot-Modules in Wormhole NoCs Isask'har Walter1
- QNoC: QoS architecture and design process for network on chip
- QNoCQNoC
- Efficient Link Capacity and QoS Design for Network-on-Chip , Isask'har Walter1
- Routing Table Minimization for Irregular Mesh NoCs The majority of current Network on Chip (NoC) architectures
- IEEETRANSACTIONS ONELECTRONDEVICES, VOL. ED-24, NO. 8, AUGUST 1977 1093 The Response of Small Photovoltaic Detectors to Uniform
- 546 IEEE TRANSACTIONS ON ELECTRONDEVICES,VOL. ED-28, NO. 5 , MAY 1981 Automated Measurement and Analysis of MIS
- IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-33, NO. 6, JUNE 1986 835 Analysis and Modeling of Floating-Gate EEPROM
- Journal of Circuits, Systems, and Computers Vol. 14, No. 3 (2005) 515532
- Hindawi Publishing Corporation VLSI Design
- 894 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 7, JULY 2008 Effective Radii of On-Chip Decoupling Capacitors
- QNoC Asynchronous Router Rostislav (Reuven) Dobkin, Ran Ginosar and Avinoam Kolodny
- IRWIN AND JOAN JACOBS CENTER FOR COMMUNICATION AND INFORMATION TECHNOLOGIES
- A Clock Tuning Circuit for System-on-Chip Yaron Elboim, Avinoam Kolodny and Ran Ginosar
- Can Hot Traces Improve Value Prediction? Assad Khamaisee(1)
- Repeater Insertion combined with LGR Methodology for on-Chip Interconnect Timing Optimization
- Optimal Resizing of Bus Wires in Layout Migration Shay Michaely1 ,
- MICRO-MODEM RELIABILITY SOLUTION FOR NOC COMMUNICATIONS Arkadiy Morgenshtein, Evgeny Bolotin, Israel Cidon, Avinoam Kolodny, Ran Ginosar
- Leveraging Symbiotic On-Die Decoupling Capacitance Michael Sotman
- Timing Optimization of Interconnect by Simultaneous Net-Ordering, Wire Sizing and Spacing
- Link Division Multiplexing (LDM) for Network-on-Chip Links Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
- Asynchronous Bit-stream Compression (ABC) Arkadiy Morgenshtein, Avinoam Kolodny, Ran Ginosar
- Power Saving in CMOS Processors by Optimal Wire Spacing Abstract Interconnect power is a significant part of dynamic
- Packet-Level Static Timing Analysis for On Chip Networks
- Performance and Power Aware CMP Thread Allocation Yaniv Ben-Itzhak, 2
- Leveraging Application-Level Requirements in the Design of a NoC for a 4G SoC -a Case Study
- 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel 978-1-4244-8682-3/10/$26.00 2010 IEEE
- Life in theLife in the Synchronous LaneSynchronous Lane
- VLSI interconnect Avinoam Kolodny
- ""SiliconSilicon WadiWadi"" 428428IsraelIsrael
- Lessons from IntelLessons from Intel Business InnovationBusiness Innovation
- IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. ED-27, NO. 3, MARCH 1980 591 a short-termtestturningonfrom1750V.(Duringnormal
- Simple Design Criterion for Maximizing Data Rate in NoC Links Anastasia Barger and David Goren
- Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization
- Power-Delay Optimization in VLSI Microprocessors by Wire Spacing
- Interconnect-Power Dissipation in a Microprocessor Intel Israel (74) Ltd.
- Challenges and Opportunities forChallenges and Opportunities for Technion and theTechnion and the
- Avinoam Kolodny Technion Israel Institute of Technology
- Abstract--Efficient module integration in Systems on Chip (SoC) is a great challenge. We present a novel automated
- 987IEEETRANSACTIONSONELECTRONDEVICES,VOL. ED-26, NO. 6 , JUNE 1979 Correspondence
- DESIGN AND MODELLING OF NETWORK ON CHIP INTERCONNECTS USING TRANSMISSION LINES
- Abstract--This paper evaluates asymmetric cluster chip multiprocessor (ACCMP) architectures as a mechanism to
- Timing-Aware Power-Optimal Ordering KONSTANTIN MOISEEV and AVINOAM KOLODNY
- Low-Leakage Repeaters for NoC Interconnects Arkadiy Morgenshtein, Israel Cidon, Avinoam Kolodny, Ran Ginosar
- Optimal Bus Sizing in Migration of Processor Design Shmuel Wimer, Shay Michaely2
- 616 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 4, AUGUST 2003 A Clock-Tuning Circuit for System-on-Chip
- EXPLORATION OF ENERGY-DELAY TRADEOFFS IN DIGITAL CIRCUIT DESIGN Yoni Aizik and Avinoam Kolodny
- Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors
- IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO. 6, DECEMBER 2003 1153 Crosstalk Noise Reduction in Synthesized
- IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.ED-27, NO. 1, JANUARY 1980 37 Properties of Ion-Implanted Junctions in
- On-die Decoupling Capacitance: Frequency Domain Analysis of Activity Radius
- The Complexity of VLSI Power-Delay Optimization by Interconnect Resizing Konstantin Moiseev (a)
- 908 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 16, NO. 7, JULY 2008 On-Chip Power Distribution Grids With
- Scheduling Multiple Multithreaded Applications on Asymmetric and Symmetric Chip Multiprocessors
- Memristor-based IMPLY Logic Design Procedure Shahar Kvatinsky, Avinoam Kolodny,
- Delay Analysis of Wormhole Based Heterogeneous NoC
- Supported by Technion Advanced Circuit Research Lab (ACRC) Efficiency Optimization of Integrated DC-DC Buck Converters
- DOI 10.1007/s11081-010-9128-9 On VLSI interconnect optimization and linear ordering
- 2010 IEEE 26-th Convention of Electrical and Electronics Engineers in Israel 978-1-4244-8682-3/10/$26.00 2010 IEEE
- Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints
- Task Scheduling Based On Thread Essence and Resource Limitations
- Centralized Adaptive Routing for NoCs Authors Name/s per 1st Affiliation (Author)
- November 2011 Avinoam Kolodny
