He, Lei - Electrical Engineering Department, University of California at Los Angeles

• Temperature-Aware Microarchitecture Kevin Skadron,
• Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction
• FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis
• Stochastic Physical Synthesis for FPGAs with Pre-routing Interconnect Uncertainty and Process Variation
• Leakage Efficient Chip-Level Dual-Vdd Assignment with Time Slack Allocation for FPGA Power Reduction
• Topological Routing to Maximize Routability for Package Substrate
• UTACO: A Unified Timing and Congestion Optimizing Algorithm for Standard Cell Global Routing*
• Wideband Modeling of RF/Analog Circuits via Hierarchical Multi-Point Model Order Reduction
• Integrity-driven Power and Signal Network Codesign Jinjun Xiong and Lei He
• Fast Buffer Insertion Considering Process Variations Jinjun Xiong
• Design Methodology and Tools for NEC Electronics' Structured ASIC ISSP
• Jan. 21, 2003Jan. 21, 2003 ASPDAC Tutorial:ASPDAC Tutorial
• Determination of Worst-Case Crosstalk Noise for Non-Switching Victims in GHz+ Buses
• Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive
• Dual-Vdd Interconnect with Chip-level Time Slack Allocation for FPGA Power Reduction
• Coupled Power and Thermal Simulation with Active Cooling
• 1498 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 8, AUGUST 2008 Dual-Vdd Buffer Insertion for Power Reduction
• Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization
• Modeling of Coplanar Waveguide for Buffered Clock Tree Jun Chen Lei He
• INTEGRATION, the VLSI journal 39 (2006) 457473 A coupling and crosstalk-considered timing-driven global
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 18, NO. 10, OCTOBER 2010 1399 Fast Analysis of a Large-Scale Inductive Interconnect
• 1496 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 8, AUGUST 2006 Wideband Passive Multiport Model Order Reduction
• ASIC/SOC 2000 Interconnect Modeling and Design for Giga-Hertz Circuits and Systems Hewlett Packard
• AN EFFICIENT FEEDBACK PROCESSINGMETHOD FOR RELAXATIONBASED FAST TIMING SIMULATION
• Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics
• Buffered Steiner Tree Construction with Wire Sizing for Interconnect Layout Optimization 3
• Design of Integrated-Circuit Interconnects with Accurate Modeling of Chemical-Mechanical Planarization
• Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
• Technical Report UCLA Engr. 04-250 University of California at Los Angeles
• Statistical Dual-Vdd Assignment for FPGA Interconnect Power Reduction
• Journal of Information & Computational Science 1: 1 (2004) 714 Available at http://www.joics.com
• Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power
• The Polygonal Contraction Heuristic for Rectilinear Steiner Tree Construction Yin Wang, Xianlong Hong, Tong Jing, Yang Yang
• Optimality and Improvement of Dynamic Voltage Scaling Algorithms for Multimedia Applications
• Journal of Information & Computational Science 1: 3 (2004) 107116 Available at http://www.joics.com
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 10, OCTOBER 2006 2023 Dual-Vdd Interconnect With Chip-Level Time Slack
• Constraint Driven I/O Planning and Placement for Chip-package Co-design
• TECHNICAL REPORT UCLA ENGR. 04-249 UNIVERSITY OF CALIFORNIA AT LOS ANGELES
• Structured ASIC, Evolution or Revolution? Kun-Cheng Wu Yu-Wen Tsai
• Estimation of Maximum Power-up Current ECE Department
• Instruction Prediction for Step Power Reduction
• Coupled Power and Thermal Simulation with Active Cooling
• FPGA Device and Architecture Evaluation Considering Process Variations
• The Department of Electrical Engineering 2010 General Information
• 2003 ASPDAC Tutorial: Power, Timing and Signal Integrity in SoC Designs
• GPE: A New Representation for VLSI Floorplan Problem Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang
• Fast Analysis of Structured Power Grid by Triangularization Based Structure Preserving Model Order Reduction
• FPGA Power Reduction Using Configurable Dual-Vdd Fei Li, Yan Lin and Lei He
• EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 11, NOVEMBER 2007 2073 there are multiple types of buffers and the candidate locations for
• Low-Power FPGA Using Pre-defined Dual-Vdd/Dual-Vt Fabrics
• IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 2, FEBRUARY 2002 183 Impact of Die-to-Die and Within-Die Parameter
• 752 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007 Field Programmability of Supply Voltages
• Power-Efficient Pulse Width Modulation DC/DC Converters with Zero Voltage Switching Control
• Power-optimal Repeater Insertion Considering Vdd and Vth as Design Freedoms
• Minimal Skew Clock Embedding Considering Time Variant Temperature Gradient
• Ramp Up/Down Functional Unit to Reduce Step Power
• An Efficient Chip-level Time Slack Allocation Algorithm for Dual-Vdd FPGA Power Reduction
• Efficient Octilinear Steiner Tree Construction Based on Spanning Graphs* , Hai Zhou2
• Simultaneous Shield Insertion and Net Ordering for Capacitive and Inductive Coupling Minimization
• Full-chip Routing Optimization with RLC Crosstalk Jinjun Xiong, Lei He, Member, IEEE
• Analytical Placement: A Linear or a Quadratic Objective Function?
• Yiyu Shi1, Jinjun Xiong2 and Lei He3 1ECE Dept., Missouri University of Science and Technology, Rolla, MO, 65409
• 726 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 4, APRIL 2008 Fashion: A Fast and Accurate Solution to
• IPR: In-Place Reconfiguration for FPGA Fault Tolerance and Rupak Majumdar2
• Power/Ground Network Aware and Row-Based Solutions to the Crosstalk Driven
• Robust On-Chip Signaling by Staggered and Twisted
• Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates
• Worst Case RLC Noise with Timing Window Constraints Electrical Engineering Department
• Acta Mathematica Sinica, English Series Sep., 2007, Vol. 23, No. 9, pp. 15771586
• 928 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 6, JUNE 2005 Short Papers_______________________________________________________________________________
• A NEW ALGORITHM FOR FLOORPLAN DESIGN.' D. F. Wong and C. L. Liu
• An Efficient Model for Frequency-Dependent On-Chip Inductance
• Floorplanning Optimization with Trajectory Piecewise-Linear Model for Pipelined Interconnects
• Determination of Worst-case Crosstalk Noise for Non-Switching Victims in GHz+ Interconnects
• pitch Average Delay (ns) Run Time (s) spacing MIN GISS/FAF GISS/VAF GISS/ELR GISS/VAF GISS/ELR
• 358 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 3, MARCH 2004 UTACO: A Unified Timing and Congestion
• A Wideband Hierarchical Circuit Reduction for Massively Coupled Interconnects Hao Yu, Lei He, Zhenyu Qi, Sheldon X.-D. Tan
• Minimal Skew Clock Synthesis Considering Time Variant Temperature Gradient
• An Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony Optimization*
• Vector Potential Equivalent Circuit Based on PEEC Inversion
• Abstract--The high complexity and time-varying workload of emerging multimedia applications poses a major challenge for
• Robust On-chip Signaling by Staggered and Twisted Bundle
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 27, NO. 10, OCTOBER 2008 1751 Exploiting Symmetries to Speed Up SAT-Based
• Joint Design-Time and Post-Silicon Optimization for Digitally Tuned Analog Circuits
• Joint Design-Time and Post-Silicon Optimization for Digitally Tuned Analog Circuits
• Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction
• Accounting for Non-linear Dependence Using Function Driven Component Analysis
• Incremental and On-demand Random Walk for Iterative Power Distribution Network Analysis
• Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction
• Device and Architecture Concurrent Optimization for FPGA Transient Soft Error Rate
• Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping
• Design, Synthesis and Evaluation of Heterogeneous FPGA with Mixed LUTs and Macro-Gates
• Exploiting Symmetry in SAT-Based Boolean Matching for Heterogeneous FPGA Technology Mapping
• Non-Linear Statistical Static Timing Analysis for Non-Gaussian Variation
• Robust Extraction of Spatial Correlation Jinjun Xiong
• SAMSON: A Generalized Second-order Arnoldi Method for Reducing Multiple Source Linear
• CDCTree: Novel Obstacle-Avoiding Routing Tree Construction based on Current Driven Circuit Model
• An Efficient Method for Terminal Reduction of Interconnect Circuits Considering Delay Variations
• Block Structure Preserving Model Order Reduction Hao Yu, Lei He, and Sheldon X.D. Tan
• Power-optimal Repeater Insertion Considering Vdd and Vth as Design Freedoms
• Power Optimal Dual-Vdd Buffered Tree Considering Buffer Stations and Blockages
• Device And Architecture Co-Optimization for FPGA Power Reduction
• A Sparsified Vector Potential Equivalent Circuit Model for Massively Coupled Interconnects Hao Yu, Lei He
• Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction Hao Yu and Lei He
• Probabilistic Congestion Model Considering Shielding for Crosstalk Reduction
• Variability-Driven Considerations in the Design of Integrated-Circuit Global Interconnects
• Full-chip Multilevel Routing for Power and Signal Integrity Jinjun Xiong and Lei He
• COUPLED POWER AND THERMAL SIMULATION AND ITS APPLICATION Weiping Liao and Lei He
• Distributed Sleep Transistor Network for Power Reduction Changbo Long
• Pre-routingEstimation of Shielding for RLC Signal Integrity* James D.Z. Ma, Arvind Parihar, and Lei Hc
• Power Modeling and Reduction of VLIW Processors Weiping Liao and Lei He
• An Efficient Analytical Model of Coupled On-chip RLC Interconnects Liang Yin and Lei He
• Am Efficient Inductance Modelingfor On-chipInterconnects Lei He', Norman Chang, Shen Lin, and 0.Sam Nakagawa
• GLOBAL INTERCONNECT SIZING AND SPACING WITH CONSIDERATION OF COUPLING CAPACITANCE
• AN EFFICIENT APPROACH TO SIMULTANEOUS TRANSISTOR AND INTERCONNECT SIZING
• Vector Potential Equivalent Circuit Based on PEEC Inversion
• ECE Technique Report. NO. ECE-2000-01. 1 Modeling and Layout Optimization for On-chip Inductive Coupling
• Special Session Challenges and Opportunities for Low Power
• Reducing Power in an FPGA via Computer-Aided Design
• Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures
• 12345678967 76486348976
• 2003 ASPDAC Tutorial: Power, Timing and Signal Integrity in SoC Designs
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS, VOL. XX, NO. YY, MONTH 2005 1 Power Modeling and Characteristics of Field
• FPGA PERFORMANCE OPTIMIZATION VIA CHIPWISE PLACEMENT CONSIDERING PROCESS VARIATIONS
• 1042 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 7, JULY 2005 Temperature and Supply Voltage Aware Performance
• Transmission Line Modeling and Synthesis for Multi-Channel Communication
• Chip and Package Power Supply Noise Analysis for SoC Design
• Thermal Via Allocation for 3D ICs Considering Temporally and Spatially Variant Thermal Power
• Diffusion-Driven Congestion Reduction for Substrate Topological Routing
• Dynamic Power and Thermal Integrity in 3D Integration Hao Yu and Lei He
• Electrical Engineering Department (Boelter Hall 6731D) University of California, Los Angeles, CA 90095
• Timing, Energy, and Thermal Performance of Three-Dimensional Integrated Circuits
• EMPIRE: An Efficient and Compact Multiple-Parameterized Model Order Reduction Method
• DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm* , Tong Jing1, 2
• Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching
• Rotational Steiner Ratio Problem Under Uniform Orientation Metrics
• FloorplanningOptimizationwith Urajectory Piecewise-LinearModel for Pipelined Interconnects.
• Clocktree RLC Extraction with Efficient Inductance Modeling Norman Chang, Shen Lin, Lei He*, O. Sam Nakagawa, and Weize Xie
• High-Level Area and Current Estimation Fei Li, Lei He, Joe Basile
• An O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree Construction in the -Geometry Plane *
• A Robust Periodic Arnoldi Shooting Algorithm for Efficient Analysis of Large-scale RF/MM ICs
• Simultaneous Shield Insertion and Net Ordering for Capacitive and
• Temperature Aware Microprocessor Floorplanning Considering Application Dependent Power Load
• SINO/SPR: SIGNAL AND POWER NET SYNTHESIS UNDER RLC MODEL
• A Min-area Solution to Performance and RLC Crosstalk Driven Global Routing Problem *
• Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design
• Data-Path Layout Design inside SOC+ , Xian-Long Hong, Yi-Ci Cai, Jing-Yu Xu, Chang-Qi Yang, Yi-Qian Zhang, Qiang Zhou, Weimin Wu
• E. Macii et al. (Eds.): PATMOS 2004, LNCS 3254, pp. 442452, 2004. Springer-Verlag Berlin Heidelberg 2004
• Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages
• POWER MODELING AND REDUCTION OF VLIW Weiping Liao and Lei He
• Electrical Engineering Department (Boelter Hall 6731D) University of California, Los Angeles, CA 90095
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. XX, NO. Y, MONTH YEAR 1 Device and Architecture Co-Optimization for FPGA
• Rewiring For Robustness , Rupak Majumdar1
• On Optimal Physical Synthesis of Sleep Transistors Changbo Long, Jinjun Xiong and Lei He
• Simultaneous Power and Thermal Integrity Driven Via Stapling in 3D ICs
• 1066 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 7, JULY 2005 Spanning Graph-Based Nonrectilinear Steiner
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 4, APRIL 2007 739 Probabilistic Transitive-Closure Ordering and Its
• DraXRouter: Global Routing in X-Architecture with Dynamic Resource Assignment* , Tong Jing1
• FULL-CHIPINTERCONNECTPOWER ESTIMATIONAND SIMULATIONCONSIDERING CONCURRENTREPEATER AND FLIP-FLOPINSERTION
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 8, AUGUST 2005 1283 [12] M. W. Beattie and L. Pileggi, "IC analyses including extracted induc-
• 366 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 3, MARCH 2004 Full-Chip Routing Optimization
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 3, MARCH 2005 319 Extended Global Routing With
• Scalable Symbolic Model Order Reduction C.-J. Richard Shi
• Stochastic Current Prediction Enabled Frequency Actuator for Runtime Resonance Noise Reduction
• QuickYield: An Efficient Global-Search Based Parametric Yield Estimation with Performance Constraints
• Fast Non-Monte-Carlo Transient Noise Analysis for High-Precision Analog/RF Circuits by
• Fault-Tolerant Resynthesis for Dual-Output LUTs Ju-Yueh Lee1
• In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He
• Current Address University of California, Los Angeles
• Circuit-Simulated Obstacle-Aware Steiner Routing
• Allocating Power Ground Vias in 3D ICs for Simultaneous Power and Thermal Integrity
• Fast Analysis of Structured Power Grid by Triangularization Based Structure Preserving Model Order Reduction
• Circuit Simulation Based Obstacle-Aware Steiner Routing Yiyu Shi, Paul Mesa, Hao Yu and Lei He
• Off-chip Decoupling Capacitor Allocation for Chip Package Co-Design
• PiCAP: A Parallel and Incremental Capacitance Extraction Considering Stochastic Process Variation
• QuickYield: An Efficient Global-Search Based Parametric Yield Estimation with Performance Constraints
• A Linear-Time Heuristic for Improving Network Partitions C.M. Fiduccia and R.M. Mattheyses
• 1518 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 15, NO. 12, DECEMBER 1996 VLSI Module Placement Based
• Compact Thermal Modeling for Temperature-Aware Design Thermal design in sub-100nm technologies will become one of the
• Performance Optimization of VLSI Interconnect Layout Jason Cong, Lei He, Cheng-Kok Koh and Patrick H. Madden
• Fabrication Technologies for Three-Dimensional Integrated Circuits Rafael Reif
• Transistor Sizing for Minimizing Power Consumption of CMOS Circuits under Delay Constraint
• Power-Efficient and Fault-Tolerant Circuits and Systems
• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--II: EXPRESS BRIEFS, VOL. 53, NO. 4, APRIL 2006 309 Obstacle-Avoiding Rectilinear Minimum-Delay
• INTEGRATION, the VLSI journal 35 (2003) 6984 An efficient hierarchical timing-driven Steiner tree algorithm
• Topological Routing to Maximize Routability for Package Substrate
• G-Tree: gravitation-direction-based rectilinear Steiner minimal tree construction considering bend reduction *
• A new multi-layer global routing flow for congestion elimination * Jinghong Liang, Xianlong Hong, Tong Jing
• FREe: A Fast Routability Estimator * Shenghua Liu, Xianlong Hong, Tong Jing, Jingyu Xu
• Average Lengths of Wire Routing under M-Architecture and X-Architecture S.-P. Shang and X.-D. Hu
• Via-Aware Global Routing for Good VLSI Manufacturability and High Yield *
• Timing-Driven Global Routing with Efficient Buffer Insertion
• An Efficient Rectilinear Steiner Minimum Tree Algorithm Based on Ant Colony Optimization*
• A Practical and Efficient Integrated System for VLSI/ULSI Physical Design *
• A Coupling and Crosstalk Considered Timing-Driven Global Routing Algorithm for High Performance Circuit Design
• A Novel Timing-Driven Global Routing Algorithm Considering Coupling Effects for High Performance Circuit Design*
• A NOVEL AND EFFICIENT TIMING-DRIVEN GLOBAL ROUTER FOR STANDARD CELL LAYOUT DESIGN BASED ON
• An O(nlogn) Algorithm for Obstacle-Avoiding Routing Tree Construction in the -Geometry Plane *
• DAC.COM KNOWLEDGE CENTER ARTICLE www.dac.com
• Department of molecular & meDical
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 13, NO. 9, SEPTEMBER 2005 1035 Circuits and Architectures for Field Programmable
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, VOL. XX, NO. Y, MONTH 2005 1 Circuits and Architectures for Field Programmable
• Vdd Programmability to Reduce FPGA Interconnect Power Fei Li, Yan Lin and Lei He
• Routing Track Duplication with Fine-Grained Power-Gating for FPGA Interconnect Power Reduction
• Simultaneous Time Slack Budgeting and Retiming for Dual-Vdd FPGA Power Reduction
• Device and Architecture Concurrent Optimization for FPGA Transient Soft Error Rate
• 11ISQED05ISQED05 Introduction to
• System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage
• 1ISQED 2005 Tutorial II From Field Solvers toFrom Field Solvers to
• An-OARSMan: Obstacle-Avoiding Routing Tree Construction with Good Length Performance *
• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 24, NO. 8, AUGUST 2005 1275 Worst Case Crosstalk Noise for Nonswitching Victims in
• Design Tools for 3-D Integrated Circuits M.I.T., Department of E.E.C.S.
• Low-Power Design for Xilinx Inc.
• SAMSON: A Generalized Second-order Arnoldi Method for Reducing Multiple Source Network
• Power Modeling and Architecture Evaluation for FPGA with Novel Circuits for Vdd Programmability
• Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation
• PERFORMANCE AND RLC CROSSTALK DRIVEN GLOBAL ROUTING* Ling Zhang1
• Structured ASICs: Opportunities and Challenges Behrooz Zahiri
• Fast Dual-Vdd Buffering Based on Interconnect Prediction and Sampling
• FORst: A 3-step heuristic for obstacle-avoiding rectilinear Steiner minimum tree construction*
• Stochastic Physical Synthesis for FPGAs with Pre-routing Interconnect Uncertainty and Process Variation
• Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction
• FedEx Packing Problem You are given a number of boxes, associated with length, width, height, value and deadline to be packed.
• Vdd Programmability to Reduce FPGA Interconnect Power Fei Li, Yan Lin and Lei He
• ELECTRICAL ENGINEERING DEPARTMENT The Henry Samueli School of Engineering and Applied Science
• Stochastic Analog Circuit Behavior Modeling by Point Estimation Method
• An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing*
• High-Level Area and Power-up Current Estimation Considering Rich Cell Library
• Towards Global Routing With RLC Crosstalk Constraints James D. Z. Ma and Lei He
• ECE Technique Report. NO. ECE200001. 1 Modeling and Layout Optimization for Onchip Inductive Coupling
• spacing crossover C i1;2 C i2;2 C i3;2 C i4;2 C i5;2 C i6;2 C i7;2 C i8;2 C i9;2 C i10;2 C i11;2 C i12;2 1.0 full 6.31 4.798 8.827 11.2 11.77 11.45 11.14 11.91 11.99 11.55 9.545 7.137
• This article appeared in a journal published by Elsevier. The attached copy is furnished to the author for internal non-commercial research
• A short version of this paper appears in the 34th Design Automation Conference Multilevel Hypergraph Partitioning
• Piece-wise Linear Model for Transmission Line with Capacitive Loading and Ramp Input
• A Fast Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits
• System Level Leakage Reduction Considering the Interdependence of Temperature and Leakage
• Power Mitigation For Nanometer FPGAs
• Optimal Wiresizing for Interconnects with Multiple Sources * Jason Cong and Lei He
• 388 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 3, MARCH 2011 Physically Justifiable Die-Level Modeling of
• Noise Driven In-Package Decoupling Capacitor Optimization for Power Integrity
• Minimal Skew Clock Embedding Considering Time Variant Temperature Gradient
• 1664 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 25, NO. 9, SEPTEMBER 2006 Modeling and Synthesis of Multiport Transmission
• Micro-architecture Performance Estimation Lucanus J. Simonson1 and Lei He2
• SHIELDING AREA OPTIMIZATION UNDER THE SOLUTION OF INTERCONNECT CROSSTALK1
• Obstacle-Avoiding Rectilinear Minimum-Delay Steiner Tree Construction towards IP-Block-Based SOC Design
• Worst Case Timing Jitter and Amplitude Noise in Differential Signaling
• Multiple Si Layer ICs: Motivation, Performance Analysis, and Design Implications Shukri J. Souri Kaustav Banerjee Amit Mehrotra1
• A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based
• Fast Non-Monte-Carlo Transient Noise Analysis for High-Precision Analog/RF Circuits by
• Henry Samueli School of Engineering and Applied Science Electrical Engineering
• IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs , Naifeng Jing2
• Wearable Assistive System Design for Fall Prevention Wenyao Xu12
• Fault-Tolerant Resynthesis with Dual-Output LUTs Ju-Yueh Lee1
• Fast Non-Monte-Carlo Transient Noise Analysis for High-Precision Analog/RF Circuits by
• This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
• University of Waterloo Department of Electrical and Computer Engineering
• TRANSACTIONS ON INFORMATION TECHNOLOGY IN BIOMEDICINE, VOL. 6, NO. 1, NOVEMBER 2011 1 NeuroGlasses: A Neural Sensing HealthCare
• Page 1 of 11 Ultra-Wideband Impulse Radio with Pulse Amplitude Modulation
• Energy-Efficient FPGA Configurable Logic Block (CLB)
• Abstract--Electrodes are proving to be indispensable in the field of neural engineering. While MRI and EEG's
• Modeling and Design for Beyond-the-Die Power Integrity Electrical and Computer Engineering Dept., Missouri University of Science and Technology, Rolla, MO, 65401
• QuickYield: An Efficient Global-Search Based Parametric Yield Estimation with Performance Constraints
• Page 1 of 8 EE215B Spring 2011 Project Report
• A Subsampling UWB Radio Architecture By Analytic Signaling
• IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs , Naifeng Jing2
• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, VOL. 6, NO. 1, JANUARY 2011 1 A Parallel and Incremental Extraction of Variational
• A Universal State-of-Charge Algorithm for Batteries Bingjun Xiao Yiyu Shi Lei He
• Stochastic Analog Circuit Behavior Modeling by Point Estimation Method
• The Impact of a Wideband Channel on UWB System Design
• In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He
• Abstract--with recent aggressive technology scaling, many process variations have been introduced in CMOS technologies.
• A Fast Estimation of SRAM Failure Rate Using Probability Collectives
• Mitigating FPGA Interconnect Soft Errors by In-Place LUT Inversion
• Los Angeles, California, May 6 -9, 2012 A Behavioral Algorithm for State of Charge Estimation
• 1372 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS--I: REGULAR PAPERS, VOL. 58, NO. 6, JUNE 2011 In-Place FPGA Retiming for Mitigation of Variational
• RALF: Reliability Analysis for Logic Faults --An Exact Algorithm and Its Applications
• UNIVERSITY OF WATERLOO FACULTY OF ENGINEERING
• DESIGNMETHODSINSUB-MICRONTECHNOLOGIES Yan Lin and Lei He
• Foundations and Trends R Electronic Design Automation
• Mitigating FPGA Interconnect Soft Errors by In-Place LUT Inversion
• EE215A -Fall 2010 Analog Integrated Circuit Design
• This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1
• A Fast Non-Monte-Carlo Yield Analysis and Optimization by Stochastic Orthogonal Polynomials
• 508 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011 Runtime Resonance Noise Reduction with Current
• Acceleration of Multi-agent Simulation on FPGAs Lintao Cui, Jing Chen, Yu Hu
• PiCAP: A Parallel and Incremental Capacitance Extraction Considering Stochastic Process Variation