- A Novel Technique Towards Eliminating the Global Clock in VLSI G. Hazari M. P. Desai
- Timing Analysis of Asynchronous Systems Using Time Separation of Events
- A SelfTimed RealTime Sorting Network \Lambda (in Proceedings of International Conference on Computer Design, October 1998)
- Layoutdriven Logic Optimization R. Carragher, R. Murgai S. Chakraborty \Lambda M. R. Prasad \Lambda A. Srivastava \Lambda N. Vemuri \Lambda
- Interface Design for Rationally Clocked GALS Systems Joycee Mekie 1 Supratik Chakraborty 1 Girish Venkataramani 2 P. S. Thiagarajan 3
- E#cient Guided Symbolic Reachability Using Reachability Expressions
- Reasoning about Synchronization Techniques in GALS Systems: A Uni ed Approach
- Approximate Symbolic Reachability of Networks of Transition Systems
- Bottomup Shape Analysis Bhargav S. Gulavani + , Supratik Chakraborty + , G. Ramalingam # ,
- Practical Timing Analysis of Asynchronous Circuits Using Time Separation of Events \Lambda
- A Scalable Symbolic Simulator for Verilog RTL Sasidhar Sunkari # , Supratik Chakraborty + , Vivekananda Vedula # and Kailasnath Maneparambil
- Approximate Algorithms for Time Separation of Events \Lambda Supratik Chakraborty David L. Dill
- Layout-driven Logic Optimization R. Carragher R. Murgai S. Chakraborty T. Shibuya Y. Kanazawa
- Layoutdriven Timing Optimization by Generalized De Morgan Transform Supratik Chakraborty
- Reasoning about Synchronization in GALS Systems Supratik Chakraborty, Joycee Mekie and Dinesh K. Sharma
- Approximate Time Separation of Events in Practice \Lambda Supratik Chakraborty y Pasupathi A. Subrahmanyam z David L. Dill y
- A SelfTimed RealTime Sorting Network Kenneth Y. Yun, Member, IEEE, Kevin W. James, Student Member, IEEE, Robert H. FairlieCuninghame,
- On minimal odd rankings for Buchi complementation #
- Bounded Validity Checking of Interval Duration Logic
- POLYNOMIALTIME TECHNIQUES FOR APPROXIMATE TIMING ANALYSIS OF
- Evaluation of pausible clocking for interfacing high speed IP cores in GALS Joycee Mekie Supratik Chakraborty Dinesh K. Sharma
- Timing Analysis for Extended BurstMode Circuits \Lambda Supratik Chakraborty y
- More Accurate PolynomialTime MinMax Timing Simulation \Lambda Supratik Chakraborty David L. Dill
- Automatically Refining Abstract Interpretations Bhargav S. Gulavani # Supratik Chakraborty # Aditya V. Nori +
- Practical Timing Analysis of Asynchronous Systems Using Time Separation of Events \Lambda
- Bounding Variance and Expectation of Longest Path Lengths in DAGs Je# Edmonds # Supratik Chakraborty +
- Efficient Algorithms for Approximate Time Separation of Events
- Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delays Supratik Chakraborty
- Automatically Refining Abstract Interpretations Bhargav S. Gulavani # Supratik Chakraborty # Aditya V. Nori + Sriram K.
- MinMax Timing Analysis and An Application to Asynchronous Circuits
- Layoutdriven Timing Optimization by Generalized DeMorgan Supratik Chakraborty Rajeev Murgai
- Complexity of Minimumdelay Gate Resizing Supratik Chakraborty Rajeev Murgai
