
- Abstract--As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the
- Design and Fabrication of a MEMS Capacitive Chemical Sensor System
- DESIGN OF AN INTEGRATED HALF-CYCLE DELAY LINE DUTY CYCLE CORRECTOR DELAY-LOCKED LOOP
- Main Memory with Proximity Communication A Wide I/O DRAM Architecture
- A nascent class of memory cells based on magnetic-and glass-based materials display resistive
- Pre-print: 2003 IEEE University/Government/Industry Microelectronics (UGIM) Symposium Abstract--The effects of noise on gate oxide reliability were
- High voltage pulse generation using current mode second breakdown in a bipolar junction transistor
- Field-Programmable Gate Array in Miniature Ion Mobility Spectrometer Sensor System , Jon Cole1
- An In-Situ Ion Mobility Spectrometer Sensor System for Detecting Gaseous VOCs in Unsaturated Soils
- DESIGN AND FABRICATION OF A MEMS CHEMICAPACITIVE SENSOR FOR THE DETECTION OF VOLATILE ORGANIC COMPOUNDS
- Boise State UniversityBoise State University Ion Mobility SpectrometerIon Mobility Spectrometer
- CMOSedu.com, R. Jacob Baker The Baker ADC 1
- HIGH SPEED DIGITAL CMOS INPUT BUFFER DESIGN Krishna Duvvada
- Apply\q I'ow<, MOSfET. '" "'" 0..;1" orEk<1roM: and EI"",..,."","' h,'"'....,''',.."'''
- Designing nanosecond high voltage pulse generators using power MOSFETs
- WIRELESS ACCESS IN VEHICULAR ENVIRONMENTS USING BIT TORRENT AND BARGAINING
- IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 15, NO. 5, SEPTEMBER 2000 923 Transformerless Capacitive Coupling of Gate Signals
- Degradation in CMOS inverter circuit performance as a result of gate oxide wearout iy 2.0 nm pMOSFETs was investigated using a
- METHODS FOR MEMORY TEsnNG ling Plaisted
- WIDE I/O DRAM ARCHITECTURE UTILIZING PROXIMITY COMMUNICATION Qawi IbnZayd Harvard
- DESIGN GUIDE FOR CMOS PROCESS ON-CHIP 3D INDUCTOR USING THRU-WAFER VIAS
- TMOS: A NOVEL DESIGN FOR MOSFET TECHNOLOGY Presented in Partial Fulfillment ofthe Requirements for the
- K-DELTA-1-SIGMA MODULATORS FOR WIDEBAND ANALOG-TO-DIGITAL Vishal Saxena
- Low-Voltage Bandgap Reference Design Utilizing Schottky Diodes David L. Butler and R. Jacob Baker
- Sub. i tt.d to Or . John C. Tryon
- Indirect Compensation Technique for Low-Voltage CMOS Op-amps
- ELECTROSTATIC DISCHARGE (ESD) PROTECTION IN CMOS
- DIGITALLY-TUNABLE SURFACE ACOUSTIC WAVE RESONATOR Robert Russell Hay
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 3, MARCH 2006 699 Noise-Shaping Sense Amplifier for MRAM
- Abstract--This paper discusses the design of a second-order full-feedforward K-Delta-1-Sigma (KD1S) modulator with a fast
- WIDE RANGE, LOW JITTER DELAY-LOCKED LOOP USING A GRADUATED DIGITAL DELAY LINE AND PHASE INTERPOLATOR
- Transformerless Capacitive Couplingof Gate Signals for Series Operationof Power MOS Devices
- Synthesis of Higher-Order K-Delta-1-Sigma Modulators for Wideband ADCs
- A Compact Delay-Locked Loop for Multi-Phase Non-Overlapping Clock Generation
- Integration of IC Industry Feature Sizes with University Back-End-of-Line Post Processing
- W-2W Current Steering DAC for Programming Phase Change Memory
- Abstract--As CMOS technology shrinks, the transistor speed increases enabling higher speed communications and more
- Abstract--A monolithic integrated chip-scale surface plasmon resonance (SPR) sensor is demonstrated. The device consists of a
- A New Approach to the Design, Fabrication, and Testing of Chalcogenide-Based Multi-state Phase-Change Nonvolatile
- Compensation of CMOS Op-amps using Split-Length Transistors
- Degradation (V) Time (a.u.)
- Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics M. L. Ogas1, P. M. Price2, J. Kiepert1, R. J. Baker1, G. Bersuker3, W. B. Knowlton'2
- Investigation of Circuit-Level Oxide Degradation and its Effect on CMOS Inverter Operation and MOSFET Characteristics
- Effects of Circuit-Level Stress on Inverter Performance and MOSFET Characteristics Nate Stutzke1
- Abstract -This paper discusses educating electrical engineering students so they can do
- Gate Dielectric Degradation Effects on nMOS Devices and Simple IC Building Blocks (SICBBs) Betsy Cheek1, 4
- Design and Layout of Schottky Diodes in a Standard CMOS Process Ben Rivera1
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 4, APRIL 1999 565 A Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM
- A Windows Based Integrated Circuit Design Tool for Distance Education R. Jacob Baker
- A CMOS Standard-Cell Library for the PC-based LASI Layout System
- Process and Temperature Performance of a CMOS Beta-Multiplier Voltage Reference
- ,v,,,,,,,. ;:'CI. lechnol. 6 (1995) 1631-1633. Printed in the UK DESIGN NOTE
- CMOS transconductor VCO with adjust~bia operating and centre frequencies
- Time domain operation of the TRAPATT diode for picosecond-kilovolt pulse generation
- Meas. Sci. Technol. 5 (1994) 408-411. Printed in the UK Sweep circuit design for a picosecond
- BRIEF contributions in any field ofinstrumentation or technique within the scope of the journal should be submitted for this section. Contributions should in general not exceed 500 words.
- levels, the large change in the carrier density results in both large linear as well as large nonlinear chirp. If an appropriate
- '. stacking power MOSFETs for use in high speed instrumentation R. J. Baker and B. P. Johnson
- Meas. Sci. Technol. 3 (1992) 775-777. Printed in the. UK DESIGN NOTE
- IEEE TRA~"SACTlO0:S ON INSTRU:vIEl\TATlON AND MEASUREMENT. VOL. 40. NO.3. JUl\E 1'191 Input signal ; 500 jJV
- DESIGN IDEAS Step-recovery diodes sharpen pulses
- A THREE DIMENSIONAL NUMERICAL SIMULATION OF SHORT CHANNEL MOSFETS WITH THE EFFECTS OF
- HIGH-VOLTAGE PROGRAMMABLE DELTA-SIGMA MODULATION VOLTAGE-CONTROL CIRCUIT
- LOW-VOLTAGE CMOS TEMPERATURE SENSOR DESIGN USING SCHOTTKY DIODE-BASED REFERENCES
- NOISE-SHAPING SENSE AMPLIFIER FOR CROSS-POINT Matthew B. Leslie
- CIRCUIT DESIGN FOR AN ION MOBILITY SPECTROMETER Ravindra Puthumbaka
- READING AND WRITrNG FLASH MEMOR Y USING DELTA SIGMA MODULATION
- FLASH MEMORY SENSING USING AVERAGING Ml.lrugesh Sl.Ibramanialll
- APPLICATION OF AN ASYNCHRONOUS FIFO IN A DRAM DATA PATH
- DESIGN OF A DELAY-LOCKED LOOP WITH A DAC-CONTROLLED ANALOG DELAY LINE
- LOW-VOLTAGE BANDGAP REFERENCE DESIGN UTILIZING SCHOTTKY DIODES
- INDIRECT FEEDBACK COMPENSATION TECHNIQUES FOR MULTI-STAGE OPERATIONAL AMPLIFIERS
- Meas. Sci. Techno!. 4 (1993) 893-895. Printed in the UK DESIGN NOTE
- A Compact Delay-Locked Loop for Multi-Phase Non-Overlapping Clock Generation Chris Gagliano and R. Jacob Baker
- A Miniaturized Ion Mobility Spectrometer (IMS) Sensor for Wireless Operation. J. Hartman*, J. Baker *, M. Gribb *, H. Hill+,
- Cadsoft Eagle 4.0 Editor Tutorial Kevin Bolding
- HIGH VOLTAGE CHARGE PUMP CIRCUIT FOR AN ION MOBILITY SPECTROMETER
- Low-Voltage CMOS Temperature Sensor Design Using Schottky Diode-Based References
- DESIGN OF A CMOS 6-BIT FOLDING AND INTERPOLATING ANALOG TO DIGITAL CONVERTER
- A NOVEL ARCHITECTURE FOR ADVANCED HIGH DENSITY DYNAMIC RANDOM ACCESS MEMORIES
- COMPARISON OF ASYNCHRONOUS VS. SYNCHRONOUS DESIGN TECHNOLOGIES USING A 16-BIT BINARY ADDER
- Indirect Feedback Compensation of CMOS Op-Amps Vishal Saxena and R. Jacob Baker
- RESEARCH AND DESIGN OF LOW JITTER, WIDE LOCKING-RANGE ALL-DIGITAL
- High Speed Digital Input Buffer Circuits Krishna Duvvada, Vishal Saxena and R. Jacob Baker
- Step Response Considerations and the Design of a Suitable Step Generator for High Speed Digitizer Testing
- SENSING CIRCUIT DESIGN FOR AN ION MOBILITY SPECTROMETER Surendranath C Eruvuru
- Abstract--As CMOS technology continues to evolve, the supply voltages are decreasing while at the same time the
- A Complete Layout System for the PC David E. Boyce
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO.2, FEBRUARY 1996 271 Analog Layout Using ALAS!
- PHASE CHANGE MEMORY: ARRAY DEVELOPMENT AND SENSING CIRCUITS USING DELTA-SIGMA MODULATION
- Nanosecond switching using power MOSFETs R. J. Baker
- An Jnteractive impulse response extraction system Harry W. Li,a) Michael J. Dallabetta, and Jake Baker
- Resistive Memory Sensing Using Delta-Sigma H. Rapole, A. Rajagiri, M. Balasubramanian, K. A. Campbell, and R. J. Baker
- Abstract--Much excitement has been gen potential uses of chalcogenide glasses and o
- Systematic Design of Three-Stage Op-amps using Split-Length Compensation
- A Scalable I/O Architecture for Wide I/O DRAM Qawi Harvard and R. Jacob Baker
- TMOS: A NOVEL DESIGN FOR MOSFET TECHNOLOGY Presented in Partial Fulfillment ofthe Requirements for the
- A 2 GHz Effective Sampling Frequency K-Delta-1-Sigma Analog-to-Digital Converter